34 citations · 61 across the 23 of their papers we have counts for
10 papers · 1 filter
A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN
Yichao Zhang, Marco Bertuletti, Sergio Mazzola +2
We present HeartStream, a 64-RV-core shared-L1-memory cluster (410 GFLOP/s peak performance and 204.8 GBps L1 bandwidth) for energy-efficient AI-enhanced O-RAN. The cores and clust…
Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks
Marco Bertuletti, Yichao Zhang, Mahdi Abdollahpour +2
The fast-rising demand for wireless bandwidth requires rapid evolution of high-performance baseband processing infrastructure. Programmable many-core processors for software-define…
TROOP: At-the-Roofline Performance for Vector Processors on Low Operational Intensity Workloads
Navaneeth Kunhi Purayil, Diyou Shen, Matteo Perotti +1
The fast evolution of Machine Learning (ML) models requires flexible and efficient hardware solutions as hardwired accelerators face rapid obsolescence. Vector processors are fully…
TeraNoC: A Multi-Channel 32-bit Fine-Grained, Hybrid Mesh-Crossbar NoC for Efficient Scale-up of 1000+ Core Shared-L1-Memory Clusters
Yichao Zhang, Zexin Fu, Tim Fischer +3
A key challenge in on-chip interconnect design is to scale up bandwidth while maintaining low latency and high area efficiency. 2D-meshes scale with low wiring area and congestion…
A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-core RV Clusters for Attention-Based Model Deployment
Bowen Wang, Marco Bertuletti, Yichao Zhang +2
Attention-based models demand flexible hardware to manage diverse kernels with varying arithmetic intensities and memory access patterns. Large clusters with shared L1 memory, a co…
Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication
Samuel Riedel, Yichao Zhang, Marco Bertuletti +1
Next-generation wireless technologies (for immersive-massive communication, joint communication and sensing) demand highly parallel architectures for massive data processing. A com…
AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance
Matteo Perotti, Vincenzo Maisto, Moritz Imfeld +3
Vector processor architectures offer an efficient solution for accelerating data-parallel workloads (e.g., ML, AI), reducing instruction count, and enhancing processing efficiency.…
Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
Danilo Cammarata, Matteo Perotti, Marco Bertuletti +4
The rapid growth of AI-based Internet-of-Things applications increased the demand for high-performance edge processing engines on a low-power budget and tight area constraints. As…
TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs
Diyou Shen, Yichao Zhang, Marco Bertuletti +1
As computing demand and memory footprint of deep learning applications accelerate, clusters of cores sharing local (L1) multi-banked memory are widely used as key building blocks i…
AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
Navaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer +1
The ever-growing scale of data parallelism in today's HPC and ML applications presents a big challenge for computing architectures' energy efficiency and performance. Vector proces…