24 citations · 74 across the 14 of their papers we have counts for
16 papers
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link
Yichao Zhang, Marco Bertuletti, Chi Zhang +5
Shared L1-memory clusters of streamlined instruction processors (processing elements - PEs) are commonly used as building blocks in modern, massively parallel computing architectur…
A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN
Yichao Zhang, Marco Bertuletti, Sergio Mazzola +2
We present HeartStream, a 64-RV-core shared-L1-memory cluster (410 GFLOP/s peak performance and 204.8 GBps L1 bandwidth) for energy-efficient AI-enhanced O-RAN. The cores and clust…
Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks
Marco Bertuletti, Yichao Zhang, Mahdi Abdollahpour +2
The fast-rising demand for wireless bandwidth requires rapid evolution of high-performance baseband processing infrastructure. Programmable many-core processors for software-define…
Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication
Samuel Riedel, Yichao Zhang, Marco Bertuletti +1
Next-generation wireless technologies (for immersive-massive communication, joint communication and sensing) demand highly parallel architectures for massive data processing. A com…
Area Comparison of CHERIoT and PMP in Ibex
Samuel Riedel, Marno van der Maas, John Thomson +2
Memory safety is a critical concern for modern embedded systems, particularly in security-sensitive applications. This paper explores the area impact of adding memory safety extens…
A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR
Yichao Zhang, Marco Bertuletti, Chi Zhang +3
We introduce an open-source architecture for next-generation Radio-Access Network baseband processing: 1024 latency-tolerant 32-bit RISC-V cores share 4 MiB of L1 memory via an ult…
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios
Yichao Zhang, Marco Bertuletti, Samuel Riedel +3
Radio Access Networks (RAN) workloads are rapidly scaling up in data processing intensity and throughput as the 5G (and beyond) standards grow in number of antennas and sub-carrier…
Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters
Sergio Mazzola, Samuel Riedel, Luca Benini
Systolic arrays and shared-L1-memory manycore clusters are commonly used architectural paradigms that offer different trade-offs to accelerate parallel workloads. While the first e…
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation
Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano +2
Extensive polling in shared-memory manycore systems can lead to contention, decreased throughput, and poor energy efficiency. Both lock implementations and the general-purpose atom…
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency
Matteo Perotti, Samuel Riedel, Matheus Cavalcante +1
The ever-increasing computational and storage requirements of modern applications and the slowdown of technology scaling pose major challenges to designing and implementing efficie…
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster
Marco Bertuletti, Samuel Riedel, Yichao Zhang +2
Synchronization is likely the most critical performance killer in shared-memory parallel programs. With the rise of multi-core and many-core processors, the relative impact on perf…
A High-performance, Energy-efficient Modular DMA Engine Architecture
Thomas Benz, Michael Rogenmoser, Paul Scheffler +5
Data transfers are essential in today's computing systems as latency and complex memory access patterns are increasingly challenging to manage. Direct memory access engines (DMAEs)…
MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory
Samuel Riedel, Matheus Cavalcante, Renzo Andri +1
Shared L1 memory clusters are a common architectural pattern (e.g., in GPGPUs) for building efficient and flexible multi-processing-element (PE) engines. However, it is a common be…
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters
Matheus Cavalcante, Domenic Wüthrich, Matteo Perotti +2
While parallel architectures based on clusters of Processing Elements (PEs) sharing L1 memory are widespread, there is no consensus on how lean their PE should be. Architecting PEs…
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration
Matheus Cavalcante, Anthony Agnesina, Samuel Riedel +6
Three-dimensional integrated circuits promise power, performance, and footprint gains compared to their 2D counterparts, thanks to drastic reductions in the interconnects' length t…
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect
Matheus Cavalcante, Samuel Riedel, Antonio Pullini +1
A key challenge in scaling shared-L1 multi-core clusters towards many-core (more than 16 cores) configurations is to ensure low-latency and efficient access to the L1 memory. In th…