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20202026
most citedMemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory

24 citations · 74 across the 14 of their papers we have counts for

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eess.SP2025

Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks

Marco Bertuletti, Yichao Zhang, Mahdi Abdollahpour +2

The fast-rising demand for wireless bandwidth requires rapid evolution of high-performance baseband processing infrastructure. Programmable many-core processors for software-define…