2 citations · 2 across the 4 of their papers we have counts for
5 papers
TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation
Bardia Nadimi, Khashayar Filom, Deming Chen +1
With the rapid advancement of Large Language Models (LLMs), there is growing interest in applying them to hardware design and verification. Among these stages, design verification…
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Designing Verilog modules requires meticulous attention to correctness, efficiency, and adherence to design specifications. However, manually writing Verilog code remains a complex…
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Recently, there has been a growing interest in leveraging Large Language Models for Verilog code generation. However, the current quality of the generated Verilog code remains subo…
Forward and Reverse Converters for the Moduli-Set
Ghassem Jaberipur, Bardia Nadimi, R. Kazemi +1
Modulo- adders have recently been implemented using the regular parallel prefix (RPP) architecture, matching the speed of the widely used modulo-$(2^q \pm 1)…
Mining SoC Message Flows with Attention Model
Md Rubel Ahmed, Bardia Nadimi, Hao Zheng
High-quality system-level message flow specifications are necessary for comprehensive validation of system-on-chip (SoC) designs. However, manual development and maintenance of suc…