25 citations · 36 across the 9 of their papers we have counts for
10 papers
A Survey on LLM-Integrated Hardware Design Verification
Hao Zheng, Jaime Rafael Imperial, Bardia Nadimi +1
Large language models (LLMs) are increasingly being integrated into hardware verification to automate specification interpretation, verification-artifact generation, debugging, for…
TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation
Bardia Nadimi, Khashayar Filom, Deming Chen +1
With the rapid advancement of Large Language Models (LLMs), there is growing interest in applying them to hardware design and verification. Among these stages, design verification…
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Designing Verilog modules requires meticulous attention to correctness, efficiency, and adherence to design specifications. However, manually writing Verilog code remains a complex…
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Recently, there has been a growing interest in leveraging Large Language Models for Verilog code generation. However, the current quality of the generated Verilog code remains subo…
Forward and Reverse Converters for the Moduli-Set
Ghassem Jaberipur, Bardia Nadimi, R. Kazemi +1
Modulo- adders have recently been implemented using the regular parallel prefix (RPP) architecture, matching the speed of the widely used modulo-$(2^q \pm 1)…
Inferring Message Flows From System Communication Traces
Bardia Nadimi, Hao Zheng
This paper proposes a novel method for automatically inferring message flow specifications from the communication traces of a system-on-chip (SoC) design that captures messages exc…
A Multi-Expert Large Language Model Architecture for Verilog Code Generation
Bardia Nadimi, Hao Zheng
Recently, there has been a surging interest in using large language models (LLMs) for Verilog code generation. However, the existing approaches are limited in terms of the quality…
Modulo- Arithmetic via Two Parallel n-bit Residue Channels
Ghassem Jaberipur, Bardia Nadimi, Jeong-A Lee
Augmenting the balanced residue number system moduli-set , with the co-prime modulo , increases the dynamic range (DR) by around 70%.…
AutoModel: Automatic Synthesis of Models from Communication Traces of SoC Designs
Md Rubel Ahmed, Bardia Nadimi, Hao Zheng
Modeling system-level behaviors of intricate System-on-Chip (SoC) designs is crucial for design analysis, testing, and validation. However, the complexity and volume of SoC traces…
Mining SoC Message Flows with Attention Model
Md Rubel Ahmed, Bardia Nadimi, Hao Zheng
High-quality system-level message flow specifications are necessary for comprehensive validation of system-on-chip (SoC) designs. However, manual development and maintenance of suc…