25 citations · 36 across the 9 of their papers we have counts for
5 papers · 1 filter
A Survey on LLM-Integrated Hardware Design Verification
Hao Zheng, Jaime Rafael Imperial, Bardia Nadimi +1
Large language models (LLMs) are increasingly being integrated into hardware verification to automate specification interpretation, verification-artifact generation, debugging, for…
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Designing Verilog modules requires meticulous attention to correctness, efficiency, and adherence to design specifications. However, manually writing Verilog code remains a complex…
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Recently, there has been a growing interest in leveraging Large Language Models for Verilog code generation. However, the current quality of the generated Verilog code remains subo…
Forward and Reverse Converters for the Moduli-Set
Ghassem Jaberipur, Bardia Nadimi, R. Kazemi +1
Modulo- adders have recently been implemented using the regular parallel prefix (RPP) architecture, matching the speed of the widely used modulo-$(2^q \pm 1)…
Modulo- Arithmetic via Two Parallel n-bit Residue Channels
Ghassem Jaberipur, Bardia Nadimi, Jeong-A Lee
Augmenting the balanced residue number system moduli-set , with the co-prime modulo , increases the dynamic range (DR) by around 70%.…