3 citations · 6 across the 15 of their papers we have counts for
18 papers
Inverse Design of Finite-State Channels by Dynamic Measure Matching
Lav R. Varshney
Inspired by the optimization approach to biology, we formulate an inverse problem for communication with memory: construct a finite-state channel for which a given signaling behavi…
TALLOP: Joint Optimization of Local Training and Communication Compression for Time-Constrained Federated Learning
Honoka Anada, Yafei Ou, Shinya Takamaeda-Yamazaki
Minimizing the wall-clock time required to reach a target accuracy is crucial in federated learning (FL), where many applications require frequent model updates as data distributio…
Annotation-Driven Migration of CUDA Programs to Tenstorrent Blackhole
Ayumi Ohno, Shinya Takamaeda-Yamazaki
Tenstorrent Blackhole combines distributed local memories, explicit inter-core communication, and Tensix cores decoupling data movement from computation. CUDA offers a substantial…
CARVY-FL: Client Anticlustering for Robust Voting in Provably Secure Federated Learning
Masaki Nakada, Honoka Anada, Tatsuya Kaneko +3
Federated learning (FL) enables collaborative training without directly sharing raw data, but remains vulnerable to malicious clients. Voting-based FL improves robustness by partit…
Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding
Daichi Tokuda, Tatsuya Kubo, Ismail Emir Yuksel +8
Vector-scalar comparison is a fundamental computation primitive that compares each element in a vector against a single scalar value. It is widely used in various data-intensive wo…
PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems
Daichi Tokuda, İsmail Emir Yüksel, Tatsuya Kubo +7
Processing-using-DRAM (PuD) is a promising computation paradigm that alleviates frequent data movement between main memory and processing units by using each DRAM column as a compu…
Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators
Izumi Tanaka, Ken Sakayori, Shinya Takamaeda-Yamazaki +1
High-level synthesis (HLS) is a powerful tool for developing efficient hardware accelerators that rely on specialized memory systems to achieve sufficient on-chip data reuse and of…
PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM
Tatsuya Kubo, Daichi Tokuda, Lei Qu +2
Recently, practical analog in-memory computing has been realized using unmodified commercial DRAM modules. The underlying Processing-Using-DRAM (PUD) techniques enable high-through…
TRIP-Shapley: Propagation-Aware Contribution Attribution Framework for Peer-to-Peer Federated Learning
Honoka Anada, Tatsuya Kaneko, Yafei Ou +1
Contribution attribution is a fundamental problem in federated learning (FL), yet it remains challenging in peer-to-peer FL (P2PFL), where participant influence propagates through…
PRIOT: Pruning-Based Integer-Only Transfer Learning for Embedded Systems
Honoka Anada, Sefutsu Ryu, Masayuki Usui +2
On-device transfer learning is crucial for adapting a common backbone model to the unique environment of each edge device. Tiny microcontrollers, such as the Raspberry Pi Pico, are…
MVDRAM: Enabling GeMV Execution in Unmodified DRAM for Low-Bit LLM Acceleration
Tatsuya Kubo, Daichi Tokuda, Tomoya Nagatani +4
General matrix-vector multiplication (GeMV) remains a critical latency bottleneck in large language model (LLM) inference, even with quantized low-bit models. Processing-Using-DRAM…
RustSFQ: A Domain-Specific Language for SFQ Circuit Design
Mebuki Oishi, Sun Tanaka, Shinya Takamaeda-Yamazaki
Cell-based design of a single-flux-quantum (SFQ) digital circuit requires input-output consistency; every output signal must be consumed only once by the input of the following com…
Exploring the Versal AI Engine for 3D Gaussian Splatting
Kotaro Shimamura, Ayumi Ohno, Shinya Takamaeda-Yamazaki
Dataflow-oriented spatial architectures are the emerging paradigm for higher computation performance and efficiency. AMD Versal AI Engine is a commercial spatial architecture consi…
Accelerating Elliptic Curve Point Additions on Versal AI Engine for Multi-scalar Multiplication
Ayumi Ohno, Kotaro Shimamura, Shinya Takamaeda-Yamazaki
Multi-scalar multiplication (MSM) is crucial in cryptographic applications and computationally intensive in zero-knowledge proofs. MSM involves accumulating the products of scalars…
Federated Learning with Relative Fairness
Shogo Nakakita, Tatsuya Kaneko, Shinya Takamaeda-Yamazaki +1
This paper proposes a federated learning framework designed to achieve \textit{relative fairness} for clients. Traditional federated learning frameworks typically ensure absolute f…
PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation
Wenlun Zhang, Shimpei Ando, Yung-Chin Chen +3
Approximate computing emerges as a promising approach to enhance the efficiency of compute-in-memory (CiM) systems in deep neural network processing. However, traditional approxima…
HALO-CAT: A Hidden Network Processor with Activation-Localized CIM Architecture and Layer-Penetrative Tiling
Yung-Chin Chen, Shimpei Ando, Daichi Fujiki +2
To address the 'memory wall' problem in NN hardware acceleration, we introduce HALO-CAT, a software-hardware co-design optimized for Hidden Neural Network (HNN) processing. HALO-CA…
MP-GELU Bayesian Neural Networks: Moment Propagation by GELU Nonlinearity
Yuki Hirayama, Sinya Takamaeda-Yamazaki
Bayesian neural networks (BNNs) have been an important framework in the study of uncertainty quantification. Deterministic variational inference, one of the inference methods, util…