3 citations · 6 across the 15 of their papers we have counts for
7 papers · 1 filter
Inverse Design of Finite-State Channels by Dynamic Measure Matching
Lav R. Varshney
Inspired by the optimization approach to biology, we formulate an inverse problem for communication with memory: construct a finite-state channel for which a given signaling behavi…
TALLOP: Joint Optimization of Local Training and Communication Compression for Time-Constrained Federated Learning
Honoka Anada, Yafei Ou, Shinya Takamaeda-Yamazaki
Minimizing the wall-clock time required to reach a target accuracy is crucial in federated learning (FL), where many applications require frequent model updates as data distributio…
Annotation-Driven Migration of CUDA Programs to Tenstorrent Blackhole
Ayumi Ohno, Shinya Takamaeda-Yamazaki
Tenstorrent Blackhole combines distributed local memories, explicit inter-core communication, and Tensix cores decoupling data movement from computation. CUDA offers a substantial…
CARVY-FL: Client Anticlustering for Robust Voting in Provably Secure Federated Learning
Masaki Nakada, Honoka Anada, Tatsuya Kaneko +3
Federated learning (FL) enables collaborative training without directly sharing raw data, but remains vulnerable to malicious clients. Voting-based FL improves robustness by partit…
Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding
Daichi Tokuda, Tatsuya Kubo, Ismail Emir Yuksel +8
Vector-scalar comparison is a fundamental computation primitive that compares each element in a vector against a single scalar value. It is widely used in various data-intensive wo…
PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems
Daichi Tokuda, İsmail Emir Yüksel, Tatsuya Kubo +7
Processing-using-DRAM (PuD) is a promising computation paradigm that alleviates frequent data movement between main memory and processing units by using each DRAM column as a compu…
Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators
Izumi Tanaka, Ken Sakayori, Shinya Takamaeda-Yamazaki +1
High-level synthesis (HLS) is a powerful tool for developing efficient hardware accelerators that rely on specialized memory systems to achieve sufficient on-chip data reuse and of…