19 citations · 29 across the 12 of their papers we have counts for
14 papers
VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
Raghu Vamshi Hemadri, Jitendra Bhandari, Andre Nakkab +5
Modern chip design is complex, and there is a crucial need for early-stage prediction of key design-quality metrics like timing and routing congestion directly from Verilog code (a…
SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design
Zeng Wang, Minghao Shao, Rupesh Karn +6
Large Language Models (LLMs) offer transformative capabilities for hardware design automation, particularly in Verilog code generation. However, they also pose significant data sec…
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction
Luca Collini, Jitendra Bhandari, Chiara Muscari Tomajoli +6
In the modern global Integrated Circuit (IC) supply chain, protecting intellectual property (IP) is a complex challenge, and balancing IP loss risk and added cost for theft counter…
VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
Zeng Wang, Minghao Shao, Jitendra Bhandari +5
Large Language Models (LLMs) have revolutionized code generation, achieving exceptional results on various established benchmarking frameworks. However, concerns about data contami…
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
Zeng Wang, Minghao Shao, Mohammed Nabeel +7
Large language models (LLMs) offer significant potential for coding, yet fine-tuning (FT) with curated data is essential for niche languages like Verilog. Using proprietary intelle…
RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
Lakshmi Likhitha Mankali, Jitendra Bhandari, Manaar Alam +4
Large language models (LLMs) have demonstrated remarkable potential with code generation/completion tasks for hardware design. In fact, LLM-based hardware description language (HDL…
Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
Jitendra Bhandari, Vineet Bhat, Yuheng He +3
Masala-CHAI is a fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists. It addresses a…
SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions
Jitendra Bhandari, Rajat Sadhukhan, Prashanth Krishnamurthy +2
A globally distributed IC supply chain brings risks due to untrusted third parties. The risks span inadvertent use of hardware Trojan (HT), inserted Intellectual Property (3P-IP) o…
ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search
Jitendra Bhandari, Animesh Basak Chowdhury, Mohammed Nabeel +4
Power side-channel (PSC) analysis is pivotal for securing cryptographic hardware. Prior art focused on securing gate-level netlists obtained as-is from chip design automation, negl…
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
Jitendra Bhandari, Johann Knechtel, Ramesh Narayanaswamy +2
This work investigates the potential of tailoring Large Language Models (LLMs), specifically GPT3.5 and GPT4, for the domain of chip testing. A key aspect of chip design is functio…
Lightweight Countermeasures Against Static Power Side-Channel Attacks
Jitendra Bhandari, Mohammed Nabeel, Likhitha Mankali +3
This paper presents a novel defense strategy against static power side-channel attacks (PSCAs), a critical threat to cryptographic security. Our method is based on (1) carefully tu…
ALICE: An Automatic Design Flow for eFPGA Redaction
Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari +6
Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect th…
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction
Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan +6
Semiconductor design houses rely on third-party foundries to manufacture their integrated circuits (IC). While this trend allows them to tackle fabrication costs, it introduces sec…
Exploring eFPGA-based Redaction for IP Protection
Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan +6
Recently, eFPGA-based redaction has been proposed as a promising solution for hiding parts of a digital design from untrusted entities, where legitimate end-users can restore funct…