19 citations · 28 across the 10 of their papers we have counts for
8 papers · 1 filter
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction
Luca Collini, Jitendra Bhandari, Chiara Muscari Tomajoli +6
In the modern global Integrated Circuit (IC) supply chain, protecting intellectual property (IP) is a complex challenge, and balancing IP loss risk and added cost for theft counter…
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
Zeng Wang, Minghao Shao, Mohammed Nabeel +7
Large language models (LLMs) offer significant potential for coding, yet fine-tuning (FT) with curated data is essential for niche languages like Verilog. Using proprietary intelle…
RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
Lakshmi Likhitha Mankali, Jitendra Bhandari, Manaar Alam +4
Large language models (LLMs) have demonstrated remarkable potential with code generation/completion tasks for hardware design. In fact, LLM-based hardware description language (HDL…
SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions
Jitendra Bhandari, Rajat Sadhukhan, Prashanth Krishnamurthy +2
A globally distributed IC supply chain brings risks due to untrusted third parties. The risks span inadvertent use of hardware Trojan (HT), inserted Intellectual Property (3P-IP) o…
ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search
Jitendra Bhandari, Animesh Basak Chowdhury, Mohammed Nabeel +4
Power side-channel (PSC) analysis is pivotal for securing cryptographic hardware. Prior art focused on securing gate-level netlists obtained as-is from chip design automation, negl…
Lightweight Countermeasures Against Static Power Side-Channel Attacks
Jitendra Bhandari, Mohammed Nabeel, Likhitha Mankali +3
This paper presents a novel defense strategy against static power side-channel attacks (PSCAs), a critical threat to cryptographic security. Our method is based on (1) carefully tu…