36 citations · 109 across the 7 of their papers we have counts for
7 papers
Microarchitectural comparison and in-core modeling of state-of-the-art CPUs: Grace, Sapphire Rapids, and Genoa
Jan Laukemann, Georg Hager, Gerhard Wellein
With Nvidia's release of the Grace Superchip, all three big semiconductor companies in HPC (AMD, Intel, Nvidia) are currently competing in the race for the best CPU. In this work w…
CloverLeaf on Intel Multi-Core CPUs: A Case Study in Write-Allocate Evasion
Jan Laukemann, Thomas Gruber, Georg Hager +2
In this paper we analyze the MPI-only version of the CloverLeaf code from the SPEChpc 2021 benchmark suite on recent Intel Xeon "Ice Lake" and "Sapphire Rapids" server CPUs. We obs…
MD-Bench: Engineering the in-core performance of short-range molecular dynamics kernels from state-of-the-art simulation packages
Rafael Ravedutti Lucio Machado, Jan Eitzinger, Jan Laukemann +3
Molecular dynamics (MD) simulations provide considerable benefits for the investigation and experimentation of systems at atomic level. Their usage is widespread into several resea…
ECM modeling and performance tuning of SpMV and Lattice QCD on A64FX
Christie Alappat, Nils Meyer, Jan Laukemann +4
The A64FX CPU is arguably the most powerful Arm-based processor design to date. Although it is a traditional cache-based multicore processor, its peak performance and memory bandwi…
Performance Modeling of Streaming Kernels and Sparse Matrix-Vector Multiplication on A64FX
Christie L. Alappat, Jan Laukemann, Thomas Gruber +4
The A64FX CPU powers the current number one supercomputer on the Top500 list. Although it is a traditional cache-based multicore processor, its peak performance and memory bandwidt…
Automatic Throughput and Critical Path Analysis of x86 and ARM Assembly Kernels
Jan Laukemann, Julian Hammer, Georg Hager +1
Useful models of loop kernel runtimes on out-of-order architectures require an analysis of the in-core performance behavior of instructions and their dependencies. While an instruc…
Automated Instruction Stream Throughput Prediction for Intel and AMD Microarchitectures
Jan Laukemann, Julian Hammer, Johannes Hofmann +2
An accurate prediction of scheduling and execution of instruction streams is a necessary prerequisite for predicting the in-core performance behavior of throughput-bound loop kerne…