Automatic Throughput and Critical Path Analysis of x86 and ARM Assembly Kernels
arXiv:1910.00214 · doi:10.1109/PMBS49563.2019.00006
Abstract
Useful models of loop kernel runtimes on out-of-order architectures require an analysis of the in-core performance behavior of instructions and their dependencies. While an instruction throughput prediction sets a lower bound to the kernel runtime, the critical path defines an upper bound. Such predictions are an essential part of analytic (i.e., white-box) performance models like the Roofline and Execution-Cache-Memory (ECM) models. They enable a better understanding of the performance-relevant interactions between hardware architecture and loop code. The Open Source Architecture Code Analyzer (OSACA) is a static analysis tool for predicting the execution time of sequential loops. It previously supported only x86 (Intel and AMD) architectures and simple, optimistic full-throughput execution. We have heavily extended OSACA to support ARM instructions and critical path prediction including the detection of loop-carried dependencies, which turns it into a versatile cross-architecture modeling tool. We show runtime predictions for code on Intel Cascade Lake, AMD Zen, and Marvell ThunderX2 micro-architectures based on machine models from available documentation and semi-automatic benchmarking. The predictions are compared with actual measurements.
arXiv comment6 pages, 3 figures
References in corpus (4)
- Quantifying performance bottlenecks of stencil computations using the Execution-Cache-Memory model
- uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
- Automated Instruction Stream Throughput Prediction for Intel and AMD Microarchitectures
- Kerncraft: A Tool for Analytic Performance Modeling of Loop Kernels
Cited by in corpus (6)
- ALTO: Adaptive Linearized Storage of Sparse Tensors
- uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
- ECM modeling and performance tuning of SpMV and Lattice QCD on A64FX
- Performance Modeling of Streaming Kernels and Sparse Matrix-Vector Multiplication on A64FX
- Analytic Performance Modeling and Analysis of Detailed Neuron Simulations
- Facile: Fast, Accurate, and Interpretable Basic-Block Throughput Prediction