41 citations · 77 across the 12 of their papers we have counts for
13 papers
VHDL-REPOBENCH: A Repository-Level Benchmark for Evaluating Large Language Models on VHDL Design Generation
Prashanth Vijayaraghavan, Akul Malhotra, Ashutosh Jadhav +2
Large Language Models (LLMs) are increasingly applied in hardware design automation, demonstrating strong potential in generating and understanding hardware description languages.…
BLINK: Batch Normalization-based Integrity Checkpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN Accelerators
Marzia Khan, Akul Malhotra, Sumeet Kumar Gupta
In safety-critical deployments, AI hardware must remain reliable against a broad spectrum of threats such as aging, soft errors, hard faults, and adversarial attacks (e.g. progress…
Weight Transformations in Bit-Sliced Crossbar Arrays for Fault Tolerant Computing-in-Memory: Design Techniques and Evaluation Framework
Akul Malhotra, Sumeet Kumar Gupta
The deployment of deep neural networks (DNNs) on compute-in-memory (CiM) accelerators offers significant energy savings and speed-up by reducing data movement during inference. How…
ReTern: Exploiting Natural Redundancy and Sign Transformations for Enhanced Fault Tolerance in Compute-in-Memory based Ternary LLMs
Akul Malhotra, Sumeet Kumar Gupta
Ternary large language models (LLMs), which utilize ternary precision weights and 8-bit activations, have demonstrated competitive performance while significantly reducing the high…
BinSparX: Sparsified Binary Neural Networks for Reduced Hardware Non-Idealities in Xbar Arrays
Akul Malhotra, Sumeet Kumar Gupta
Compute-in-memory (CiM)-based binary neural network (CiM-BNN) accelerators marry the benefits of CiM and ultra-low precision quantization, making them highly suitable for edge comp…
SiTe CiM: Signed Ternary Computing-in-Memory for Ultra-Low Precision Deep Neural Networks
Niharika Thakuria, Akul Malhotra, Sandeep K. Thirumala +3
Ternary Deep Neural Networks (DNN) have shown a large potential for highly energy-constrained systems by virtue of their low power operation (due to ultra-low precision) with only…
Memory Faults in Activation-sparse Quantized Deep Neural Networks: Analysis and Mitigation using Sharpness-aware Training
Akul Malhotra, Sumeet Kumar Gupta
Improving the hardware efficiency of deep neural network (DNN) accelerators with techniques such as quantization and sparsity enhancement have shown an immense promise. However, th…
XNOR-VSH: A Valley-Spin Hall Effect-based Compact and Energy-Efficient Synaptic Crossbar Array for Binary Neural Networks
Karam Cho, Sumeet Kumar Gupta
Binary neural networks (BNNs) have shown an immense promise for resource-constrained edge artificial intelligence (AI) platforms as their binarized weights and inputs can significa…
FlatENN: Train Flat for Enhanced Fault Tolerance of Quantized Deep Neural Networks
Akul Malhotra, Sumeet Kumar Gupta
Model compression via quantization and sparsity enhancement has gained an immense interest to enable the deployment of deep neural networks (DNNs) in resource-constrained edge envi…
ADRA: Extending Digital Computing-in-Memory with Asymmetric Dual-Row-Activation
Akul Malhotra, Atanu K. Saha, Chunguang Wang +1
Computing in-memory (CiM) has emerged as an attractive technique to mitigate the von-Neumann bottleneck. Current digital CiM approaches for in-memory operands are based on multi-wo…
Exploiting Oxide Based Resistive RAM Variability for Bayesian Neural Network Hardware Design
Akul Malhotra, Sen Lu, Kezhou Yang +1
Uncertainty plays a key role in real-time machine learning. As a significant shift from standard deep networks, which does not consider any uncertainty formulation during its train…
All-Spin Bayesian Neural Networks
Kezhou Yang, Akul Malhotra, Sen Lu +1
Probabilistic machine learning enabled by the Bayesian formulation has recently gained significant attention in the domain of automated reasoning and decision-making. While impress…
A Novel Low Power Non-Volatile SRAM Cell with Self Write Termination
Kanika Monga, Akul Malhotra, Nitin Chaturvedi +1
A non-volatile SRAM cell is proposed for low power applications using Spin Transfer Torque-Magnetic Tunnel Junction (STT-MTJ) devices. This novel cell offers non-volatile storage,…