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20192026
most citedExploiting Oxide Based Resistive RAM Variability for Bayesian Neural Network Hardware Design

41 citations · 77 across the 12 of their papers we have counts for

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7 papers · 1 filter

cs.AR2026

BLINK: Batch Normalization-based Integrity Checkpoints for In-Situ Detection and Mitigation of Diverse Weight Corruptions in DNN Accelerators

Marzia Khan, Akul Malhotra, Sumeet Kumar Gupta

In safety-critical deployments, AI hardware must remain reliable against a broad spectrum of threats such as aging, soft errors, hard faults, and adversarial attacks (e.g. progress…

cs.AR2025

Weight Transformations in Bit-Sliced Crossbar Arrays for Fault Tolerant Computing-in-Memory: Design Techniques and Evaluation Framework

Akul Malhotra, Sumeet Kumar Gupta

The deployment of deep neural networks (DNNs) on compute-in-memory (CiM) accelerators offers significant energy savings and speed-up by reducing data movement during inference. How…

cs.AR2025

ReTern: Exploiting Natural Redundancy and Sign Transformations for Enhanced Fault Tolerance in Compute-in-Memory based Ternary LLMs

Akul Malhotra, Sumeet Kumar Gupta

Ternary large language models (LLMs), which utilize ternary precision weights and 8-bit activations, have demonstrated competitive performance while significantly reducing the high…

cs.AR2024

BinSparX: Sparsified Binary Neural Networks for Reduced Hardware Non-Idealities in Xbar Arrays

Akul Malhotra, Sumeet Kumar Gupta

Compute-in-memory (CiM)-based binary neural network (CiM-BNN) accelerators marry the benefits of CiM and ultra-low precision quantization, making them highly suitable for edge comp…

cs.AR2024

SiTe CiM: Signed Ternary Computing-in-Memory for Ultra-Low Precision Deep Neural Networks

Niharika Thakuria, Akul Malhotra, Sandeep K. Thirumala +3

Ternary Deep Neural Networks (DNN) have shown a large potential for highly energy-constrained systems by virtue of their low power operation (due to ultra-low precision) with only…

cs.AR2022

ADRA: Extending Digital Computing-in-Memory with Asymmetric Dual-Row-Activation

Akul Malhotra, Atanu K. Saha, Chunguang Wang +1

Computing in-memory (CiM) has emerged as an attractive technique to mitigate the von-Neumann bottleneck. Current digital CiM approaches for in-memory operands are based on multi-wo…

cs.AR2019

A Novel Low Power Non-Volatile SRAM Cell with Self Write Termination

Kanika Monga, Akul Malhotra, Nitin Chaturvedi +1

A non-volatile SRAM cell is proposed for low power applications using Spin Transfer Torque-Magnetic Tunnel Junction (STT-MTJ) devices. This novel cell offers non-volatile storage,…