257 citations · 483 across the 39 of their papers we have counts for
8 papers · 1 filter
Multiplier Optimization via E-Graph Rewriting
Andy Wanna, Samuel Coward, Theo Drane +2
Multiplier circuits account for significant resource usage in datapath-dominated circuit designs, and RTL designers continue to build bespoke hand-crafted multiplication arrays for…
Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference?
Cheng Zhang, Jianyi Cheng, Ilia Shumailov +2
The inference of Large language models (LLMs) requires immense computation and memory resources. To curtail these costs, quantisation has merged as a promising solution, but existi…
PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference
Marta Andronic, George A. Constantinides
Field-programmable gate arrays (FPGAs) are widely used to implement deep learning inference. Standard deep neural network inference involves the computation of interleaved linear m…
FPGA Resource-aware Structured Pruning for Real-Time Neural Networks
Benjamin Ramhorst, Vladimir Loncar, George A. Constantinides
Neural networks achieve state-of-the-art performance in image classification, speech recognition, scientific analysis and many more application areas. Due to the high computational…
Datapath Verification via Word-Level E-Graph Rewriting
Samuel Coward, Emiliano Morini, Bryan Tan +2
Formal verification of datapath circuits is challenging as they are subject to intense optimization effort in the design phase. Industrial vendors and design companies deploy equiv…
eGPU: A 750 MHz Class Soft GPGPU for FPGA
Martin Langhammer, George Constantinides
This paper introduces the eGPU, a SIMT soft processor designed for FPGAs. Soft processors typically achieve modest operating frequencies, a fraction of the headline performance cla…