activity
20072020
most citedMachine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits

15 citations · 44 across the 6 of their papers we have counts for

collaborators

6 papers

cs.AR2020★ 11 cited

Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features

Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux +2

Selective mitigation or selective hardening is an effective technique to obtain a good trade-off between the improvements in the overall reliability of a circuit and the hardware o…

cs.LG2020★ 13 cited

On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques

Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux +2

De-Rating or Vulnerability Factors are a major feature of failure analysis efforts mandated by today's Functional Safety requirements. Determining the Functional De-Rating of seque…

eess.SP2020★ 15 cited

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits

Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux +2

The Functional Failure Rate analysis of today's complex circuits is a difficult task and requires a significant investment in terms of human efforts, processing resources and tool…

cs.AR2020★ 3 cited

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Thomas Lange, Maximilien Glorieux, Dan Alexandrescu +1

With technology scaling, lower supply voltages, and higher operating frequencies clock distribution networks become more and more vulnerable to transients faults. These faults can…

cs.CR2019

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems

Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda +15

The recent trends for nanoelectronic computing systems include machine-to-machine communication in the era of Internet-of-Things (IoT) and autonomous systems, complex safety-critic…

cs.AR2007★ 2 cited

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

F. Lima Kastensmidt, L. Sterpone, L. Carro +1

Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by…