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L. Sterpone

6 papers hereh-index 273.9k citations256 works total

Matching runs newest-first, so older work may not be attached to this profile yet.

author position
  • middle author2
  • last author4

Across the 6 of 6 papers where every author was matched, so the position is known.

fields
  • cs.AR3
  • cs.CR1
  • cs.LG1
  • eess.SP1
same name
  • L. Sterpone — 1 paper, h 5

Either other researchers who publish under this name, or the same person where the external sources have not merged their records.

identity via Semantic Scholar / OpenAlex

activity
20072020
most citedMachine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits

15 citations · 44 across the 6 of their papers we have counts for

collaborators
Showing cs.ARShow all

3 papers · 1 filter

cs.AR2020★ 11 cited

Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features

Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux +2

Selective mitigation or selective hardening is an effective technique to obtain a good trade-off between the improvements in the overall reliability of a circuit and the hardware o…

cs.AR2020★ 3 cited

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Thomas Lange, Maximilien Glorieux, Dan Alexandrescu +1

With technology scaling, lower supply voltages, and higher operating frequencies clock distribution networks become more and more vulnerable to transients faults. These faults can…

cs.AR2007★ 2 cited

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

F. Lima Kastensmidt, L. Sterpone, L. Carro +1

Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by…

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Not affiliated with arXiv. Researcher data from Semantic Scholar (ODC-BY) and OpenAlex.