16 citations · 36 across the 18 of their papers we have counts for
18 papers
An Automated Framework for Generating Stealthy Cell-Embedded Hardware Trojans
Raghul Saravanan, Sudipta Paria, Sai Manoj P D +1
Hardware Trojans (HTs) pose significant threats across the Integrated Circuit (IC) design lifecycle because they can be inserted by untrusted entities at different stages under the…
GRAFT: Graphlet-Triggered Backdoor Attack on GNN-Based Hardware Security Systems
Sanaz Kazemi Abharian, Sai Manoj Pudukotai Dinakarrao
The globalization of the integrated circuit (IC) supply chain increases the risk of security threats, such as hardware Trojans (HTs) and the theft of intellectual property (IP). Gr…
Logic Solver Guided Directed Fuzzing for Hardware Designs
Raghul Saravanan, Sai Manoj P D
The ever-increasing complexity of design specifications for processors and intellectual property (IP) presents a formidable challenge for early bug detection in the modern IC desig…
Bit-Flip Fault Attack: Crushing Graph Neural Networks via Gradual Bit Search
Sanaz Kazemi Abharian, Sai Manoj Pudukotai Dinakarrao
Graph Neural Networks (GNNs) have emerged as a powerful machine learning method for graph-structured data. A plethora of hardware accelerators has been introduced to meet the perfo…
Accelerating Hardware Verification with Graph Models
Raghul Saravanan, Sreenitha Kasarapu, Sai Manoj Pudukotai Dinakarrao
The increasing complexity of modern processor and IP designs presents significant challenges in identifying and mitigating hardware flaws early in the IC design cycle. Traditional…
Optimizing Malware Detection in IoT Networks: Leveraging Resource-Aware Distributed Computing for Enhanced Security
Sreenitha Kasarapu, Sanket Shukla, Sai Manoj Pudukotai Dinakarrao
In recent years, networked IoT systems have revolutionized connectivity, portability, and functionality, offering a myriad of advantages. However, these systems are increasingly ta…
Empowering Malware Detection Efficiency within Processing-in-Memory Architecture
Sreenitha Kasarapu, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao
The widespread integration of embedded systems across various industries has facilitated seamless connectivity among devices and bolstered computational capabilities. Despite their…
Enhancing IoT Malware Detection through Adaptive Model Parallelism and Resource Optimization
Sreenitha Kasarapu, Sanket Shukla, Sai Manoj Pudukotai Dinakarrao
The widespread integration of IoT devices has greatly improved connectivity and computational capabilities, facilitating seamless communication across networks. Despite their globa…
Generative AI-Based Effective Malware Detection for Embedded Computing Systems
Sreenitha Kasarapu, Sanket Shukla, Rakibul Hassan +3
One of the pivotal security threats for the embedded computing systems is malicious software a.k.a malware. With efficiency and efficacy, Machine Learning (ML) has been widely adop…
The Emergence of Hardware Fuzzing: A Critical Review of its Significance
Raghul Saravanan, Sai Manoj Pudukotai Dinakarrao
In recent years, there has been a notable surge in attention towards hardware security, driven by the increasing complexity and integration of processors, SoCs, and third-party IPs…
A Neural Network-based SAT-Resilient Obfuscation Towards Enhanced Logic Locking
Rakibul Hassan, Gaurav Kolhe, Setareh Rafatirad +2
Logic obfuscation is introduced as a pivotal defense against multiple hardware threats on Integrated Circuits (ICs), including reverse engineering (RE) and intellectual property (I…
Adaptive-Gravity: A Defense Against Adversarial Samples
Ali Mirzaeian, Zhi Tian, Sai Manoj P D +4
This paper presents a novel model training solution, denoted as Adaptive-Gravity, for enhancing the robustness of deep neural network classifiers against adversarial examples. We c…
CAPTIVE: Constrained Adversarial Perturbations to Thwart IC Reverse Engineering
Amir Hosein Afandizadeh Zargari, Marzieh AshrafiAmiri, Minjun Seo +3
Reverse engineering (RE) in Integrated Circuits (IC) is a process in which one will attempt to extract the internals of an IC, extract the circuit structure, and determine the gate…
Deep Multi-attributed Graph Translation with Node-Edge Co-evolution
Xiaojie Guo, Liang Zhao, Cameron Nowzari +3
Generalized from image and language translation, graph translation aims to generate a graph in the target domain by conditioning an input graph in the source domain. This promising…
DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain
Shervin Roshanisefat, Hadi Mardani Kamali, Kimia Zamiri Azar +4
In this paper, we introduce DFSSD, a novel logic locking solution for sequential and FSM circuits with a restricted (locked) access to the scan chain. DFSSD combines two techniques…
Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design
Hosein Mohammadi Makrani, Farnoud Farahmand, Hossein Sayadi +6
The emergence of High-Level Synthesis (HLS) tools shifted the paradigm of hardware design by making the process of mapping high-level programming languages to hardware design such…
Estimating the Circuit Deobfuscating Runtime based on Graph Deep Learning
Zhiqian Chen, Gaurav Kolhe, Setareh Rafatirad +4
Circuit obfuscation is a recently proposed defense mechanism to protect digital integrated circuits (ICs) from reverse engineering by using camouflaged gates i.e., logic gates whos…
Computer-Aided Arrhythmia Diagnosis by Learning ECG Signal
Sai Manoj Pudukotai Dinakarrao, Matthias Wess
Electrocardiogram (ECG) is one of the non-invasive and low-risk methods to monitor the condition of the human heart. Any abnormal pattern(s) in the ECG signal is an indicative meas…