137 citations · 331 across the 17 of their papers we have counts for
18 papers
MAx-DNN: Multi-Level Arithmetic Approximation for Energy-Efficient DNN Hardware Accelerators
Vasileios Leon, Georgios Makris, Sotirios Xydis +2
Nowadays, the rapid growth of Deep Neural Network (DNN) architectures has established them as the defacto approach for providing advanced Machine Learning tasks with excellent accu…
Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space
Vasileios Leon, Elissaios Alexios Papatheofanous, George Lentaris +5
The ever-increasing demand for computational power and I/O throughput in space applications is transforming the landscape of on-board computing. A variety of Commercial-Off-The-She…
Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications
Vasileios Leon, George Lentaris, Dimitrios Soudris +2
The success of AI/ML in terrestrial applications and the commercialization of space are now paving the way for the advent of AI/ML in satellites. However, the limited processing po…
FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks
Vasileios Leon, Charalampos Bezaitis, George Lentaris +7
The advent of computationally demanding algorithms and high data rate instruments in new space applications pushes the space industry to explore disruptive solutions for on-board d…
The Unexpected Efficiency of Bin Packing Algorithms for Dynamic Storage Allocation in the Wild: An Intellectual Abstract
Christos P. Lamprakos, Sotirios Xydis, Francky Catthoor +1
Recent work has shown that viewing allocators as black-box 2DBP solvers bears meaning. For instance, there exists a 2DBP-based fragmentation metric which often correlates monotonic…
Viewing Allocators as Bin Packing Solvers Demystifies Fragmentation
Christos P. Lamprakos, Sotirios Xydis, Francky Catthoor +1
This paper presents a trace-based simulation methodology for constructing representations of workload-allocator interaction. We use two-dimensional rectangular bin packing (2DBP) a…
Energy Consumption Evaluation of Optane DC Persistent Memory for Indexing Data Structures
Manolis Katsaragakis, Christos Baloukas, Lazaros Papadopoulos +3
The Intel Optane DC Persistent Memory (DCPM) is an attractive novel technology for building storage systems for data intensive HPC applications, as it provides lower cost per byte,…
Co-Design of Approximate Multilayer Perceptron for Ultra-Resource Constrained Printed Circuits
Giorgos Armeniakos, Georgios Zervakis, Dimitrios Soudris +2
Printed Electronics (PE) exhibits on-demand, extremely low-cost hardware due to its additive manufacturing process, enabling machine learning (ML) applications for domains that fea…
Towards making the most of NLP-based device mapping optimization for OpenCL kernels
Petros Vavaroutsos, Ioannis Oroutzoglou, Dimosthenis Masouros +1
Nowadays, we are living in an era of extreme device heterogeneity. Despite the high variety of conventional CPU architectures, accelerator devices, such as GPUs and FPGAs, also app…
Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey
Giorgos Armeniakos, Georgios Zervakis, Dimitrios Soudris +1
Deep Neural Networks (DNNs) are very popular because of their high performance in various cognitive tasks in Machine Learning (ML). Recent advancements in DNNs have brought beyond…
Cross-Layer Approximation For Printed Machine Learning Circuits
Giorgos Armeniakos, Georgios Zervakis, Dimitrios Soudris +2
Printed electronics (PE) feature low non-recurring engineering costs and low per unit-area fabrication costs, enabling thus extremely low-cost and on-demand hardware. Such low-cost…
AdaPT: Fast Emulation of Approximate DNN Accelerators in PyTorch
Dimitrios Danopoulos, Georgios Zervakis, Kostas Siozios +2
Current state-of-the-art employs approximate multipliers to address the highly increased power demands of DNN accelerators. However, evaluating the accuracy of approximate DNNs is…
EDEN: A high-performance, general-purpose, NeuroML-based neural simulator
Sotirios Panagiotou, Harry Sidiropoulos, Mario Negrello +2
Modern neuroscience employs in silico experimentation on ever-increasing and more detailed neural networks. The high modelling detail goes hand in hand with the need for high model…
Automated Physics-Derived Code Generation for Sensor Fusion and State Estimation
Orestis Kaparounakis, Vasileios Tsoutsouras, Dimitrios Soudris +1
We present a new method for automatically generating the implementation of state-estimation algorithms from a machine-readable specification of the physics of a sensing system and…
BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations
Georgios Smaragdos, Georgios Chatzikonstantis, Rahul Kukreja +8
Objective: The advent of High-Performance Computing (HPC) in recent years has led to its increasing use in brain study through computational models. The scale and complexity of suc…
Network Function Virtualization based on FPGAs:A Framework for all-Programmable network devices
Christoforos Kachris, Georgios Sirakoulis, Dimitrios Soudris
Network Function Virtualization (NFV) refers to the use of commodity hardware resources as the basic platform to perform specialized network functions as opposed to specialized har…
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
M. D. Galanis, A. Milidonis, G. Theodoridis +2
In this paper, we propose a methodology for partitioning and mapping computational intensive applications in reconfigurable hardware blocks of different granularity. A generic hybr…
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck
Minas Dasygenis, Erik Brockmeyer, Bart Durinck +3
The memory subsystem has always been a bottleneck in performance as well as significant power contributor in memory intensive applications. Many researchers have presented multi-la…