Co-Design of Approximate Multilayer Perceptron for Ultra-Resource Constrained Printed Circuits

Abstract

Printed Electronics (PE) exhibits on-demand, extremely low-cost hardware due to its additive manufacturing process, enabling machine learning (ML) applications for domains that feature ultra-low cost, conformity, and non-toxicity requirements that silicon-based systems cannot deliver. Nevertheless, large feature sizes in PE prohibit the realization of complex printed ML circuits. In this work, we present, for the first time, an automated printed-aware software/hardware co-design framework that exploits approximate computing principles to enable ultra-resource constrained printed multilayer perceptrons (MLPs). Our evaluation demonstrates that, compared to the state-of-the-art baseline, our circuits feature on average 6x (5.7x) lower area (power) and less than 1% accuracy loss.

Accepted for publication by IEEE Transactions on Computers, February 2023

References in corpus (1)

• CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs

Cited by in corpus (5)

• Approximate Computing Survey, Part II: Application-Specific & Architectural Approximation Techniques and Applications
• Bespoke Approximation of Multiplication-Accumulation and Activation Targeting Printed Multilayer Perceptrons
• Embedding Hardware Approximations in Discrete Genetic-based Training for Printed MLPs
• Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks
• Reducing ADC Front-end Costs During Training of On-sensor Printed Multilayer Perceptrons