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20072025
most citedHardware Approximate Techniques for Deep Neural Network Accelerators: A Survey

137 citations · 331 across the 17 of their papers we have counts for

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Showing cs.ARShow all

6 papers · 1 filter

cs.AR2025★ 7 cited

Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space

Vasileios Leon, Elissaios Alexios Papatheofanous, George Lentaris +5

The ever-increasing demand for computational power and I/O throughput in space applications is transforming the landscape of on-board computing. A variety of Commercial-Off-The-She…

cs.AR2025★ 18 cited

Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications

Vasileios Leon, George Lentaris, Dimitrios Soudris +2

The success of AI/ML in terrestrial applications and the commercialization of space are now paving the way for the advent of AI/ML in satellites. However, the limited processing po…

cs.AR2025★ 15 cited

FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks

Vasileios Leon, Charalampos Bezaitis, George Lentaris +7

The advent of computationally demanding algorithms and high data rate instruments in new space applications pushes the space industry to explore disruptive solutions for on-board d…

cs.AR2022★ 137 cited

Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey

Giorgos Armeniakos, Georgios Zervakis, Dimitrios Soudris +1

Deep Neural Networks (DNNs) are very popular because of their high performance in various cognitive tasks in Machine Learning (ML). Recent advancements in DNNs have brought beyond…

cs.AR2007

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

M. D. Galanis, A. Milidonis, G. Theodoridis +2

In this paper, we propose a methodology for partitioning and mapping computational intensive applications in reconfigurable hardware blocks of different granularity. A generic hybr…

cs.AR2007

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck

Minas Dasygenis, Erik Brockmeyer, Bart Durinck +3

The memory subsystem has always been a bottleneck in performance as well as significant power contributor in memory intensive applications. Many researchers have presented multi-la…