activity
20162026
most citedSMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations

81 citations · 150 across the 48 of their papers we have counts for

collaborators
Showing cs.ARShow all

19 papers · 1 filter

cs.AR2026

KerColle: Unlocking Fine-Grained GPU Concurrency in Vision-Language-Action Models

Anna Li, Christina Giannoula, Nandita Vijaykumar

Vision-Language-Action (VLA) models have emerged as foundational models for next-generation robotics. High VLA inference throughput is critical for meeting the control-rate require…

cs.AR2026

DataGuard: Guaranteeing Private Training in Systolic-array Based Accelerators

Pawan Kumar Sanjaya, Christina Giannoula, Nikhil Shreekumar +6

Differential privacy (DP) and federated learning (FL) have emerged as important privacy-preserving approaches when using sensitive data to train machine learning (ML) models. FL en…

cs.AR2024★ 1 cited

Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology

Konstantinos Kanellopoulos, Konstantinos Sgouras, F. Nisa Bostanci +7

The unprecedented growth in data demand from emerging applications has turned virtual memory (VM) into a major performance bottleneck. Researchers explore new hardware/OS co-design…

cs.AR2024

ACS: Concurrent Kernel Execution on Irregular, Input-Dependent Computational Graphs

Sankeerth Durvasula, Adrian Zhao, Raymond Kiguru +3

GPUs are widely used to accelerate many important classes of workloads today. However, we observe that several important emerging classes of workloads, including simulation engines…

cs.AR2023

Architectural Support for Efficient Data Movement in Disaggregated Systems

Christina Giannoula, Kailong Huang, Jonathan Tang +4

Resource disaggregation offers a cost effective solution to resource scaling, utilization, and failure-handling in data centers by physically separating hardware devices in a serve…

cs.AR2023

DaeMon: Architectural Support for Efficient Data Movement in Disaggregated Systems

Christina Giannoula, Kailong Huang, Jonathan Tang +4

Resource disaggregation offers a cost effective solution to resource scaling, utilization, and failure-handling in data centers by physically separating hardware devices in a serve…

cs.AR2022

ALP: Alleviating CPU-Memory Data Movement Overheads in Memory-Centric Systems

Nika Mansouri Ghiasi, Nandita Vijaykumar, Geraldo F. Oliveira +7

Partitioning applications between NDP and host CPU cores causes inter-segment data movement overhead, which is caused by moving data generated from one segment (e.g., instructions,…

cs.AR2022★ 14 cited

Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings

Konstantinos Kanellopoulos, Rahul Bera, Kosta Stojiljkovic +8

Conventional virtual memory (VM) frameworks enable a virtual address to flexibly map to any physical address. This flexibility necessitates large data structures to store virtual-t…

cs.AR2022

VoxelCache: Accelerating Online Mapping in Robotics and 3D Reconstruction Tasks

Sankeerth Durvasula, Raymond Kiguru, Samarth Mathur +3

Real-time 3D mapping is a critical component in many important applications today including robotics, AR/VR, and 3D visualization. 3D mapping involves continuously fusing depth map…

cs.AR2022

RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory

Nika Mansouri Ghiasi, Mohammad Sadrosadati, Geraldo F. Oliveira +9

Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip, allowing for fine-grained connections between la…

cs.AR2022★ 13 cited

GenStore: A High-Performance and Energy-Efficient In-Storage Computing System for Genome Sequence Analysis

Nika Mansouri Ghiasi, Jisung Park, Harun Mustafa +11

Read mapping is a fundamental, yet computationally-expensive step in many genomics applications. It is used to identify potential matches and differences between fragments (called…

cs.AR2021

QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips

Ataberk Olgun, Minesh Patel, A. Giray Yağlıkçı +6

True random number generators (TRNG) sample random physical processes to create large amounts of random numbers for various use cases, including security-critical cryptographic pri…

cs.AR2021★ 1 cited

MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations

Nandita Vijaykumar, Ataberk Olgun, Konstantinos Kanellopoulos +5

This paper introduces the first open-source FPGA-based infrastructure, MetaSys, with a prototype in a RISC-V core, to enable the rapid implementation and evaluation of a wide range…

cs.AR2021★ 5 cited

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

Geraldo F. Oliveira, Juan Gómez-Luna, Lois Orosa +5

Data movement between the CPU and main memory is a first-order obstacle against improving performance, scalability, and energy efficiency in modern systems. Computer systems employ…

cs.AR2021

SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures

Christina Giannoula, Nandita Vijaykumar, Nikela Papadopoulou +7

Near-Data-Processing (NDP) architectures present a promising way to alleviate data movement costs and can provide significant performance and energy benefits to parallel applicatio…

cs.AR2020★ 2 cited

SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors

Jawad Haj-Yahya, Mohammed Alser, Jeremie Kim +4

There are three domains in a modern thermally-constrained mobile system-on-chip (SoC): compute, IO, and memory. We observe that a modern SoC typically allocates a fixed power budge…

cs.AR2018★ 2 cited

Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency

Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar +4

This paper summarizes the idea of ChargeCache, which was published in HPCA 2016 [51], and examines the work's significance and future potential. DRAM latency continues to be a crit…

cs.AR2018★ 1 cited

SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure

Hasan Hassan, Nandita Vijaykumar, Samira Khan +6

This paper summarizes the SoftMC DRAM characterization infrastructure, which was published in HPCA 2017, and examines the work's significance and future potential. SoftMC (Soft Mem…

cs.AR2016

A Framework for Accelerating Bottlenecks in GPU Execution with Assist Warps

Nandita Vijaykumar, Gennady Pekhimenko, Adwait Jog +7

Modern Graphics Processing Units (GPUs) are well provisioned to support the concurrent execution of thousands of threads. Unfortunately, different bottlenecks during execution and…