activity
20202024
most citedTinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge

47 citations · 92 across the 7 of their papers we have counts for

collaborators

8 papers

eess.SP2024★ 1 cited

ACCO: Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators

Jun Yin, Linyan Mei, Andre Guntoro +1

Spatio-Temporal Convolutional Neural Networks (ST-CNN) allow extending CNN capabilities from image processing to consecutive temporal-pattern recognition. Generally, state-of-the-a…

cs.AR2023

SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators

Victor J. B. Jung, Arne Symons, Linyan Mei +2

To meet the growing need for computational power for DNNs, multiple specialized hardware architectures have been proposed. Each DNN layer should be mapped onto the hardware with th…

cs.AR2023★ 47 cited

TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge

Vikram Jain, Sebastian Giraldo, Jaro De Roose +3

Extreme edge devices or Internet-of-thing nodes require both ultra-low power always-on processing as well as the ability to do on-demand sampling and processing. Moreover, support…

cs.AR2022★ 10 cited

Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators

Arne Symons, Linyan Mei, Steven Colleman +3

As the landscape of deep neural networks evolves, heterogeneous dataflow accelerators, in the form of multi-core architectures or chiplet-based designs, promise more flexibility an…

cs.AR2022★ 1 cited

DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling

Linyan Mei, Koen Goetschalckx, Arne Symons +1

DNN workloads can be scheduled onto DNN accelerators in many different ways: from layer-by-layer scheduling to cross-layer depth-first scheduling (a.k.a. layer fusion, or cascaded…

cs.AR2022★ 3 cited

CONVOLVE: Smart and seamless design of smart edge processors

M. Gomony, F. Putter, A. Gebregiorgis +25

With the rise of Deep Learning (DL), our world braces for AI in every edge device, creating an urgent need for edge-AI SoCs. This SoC hardware needs to support high throughput, rel…

cs.DC2021★ 16 cited

Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representation

Ehab M. Ibrahim, Linyan Mei, Marian Verhelst

Reduced-precision and variable-precision multiply-accumulate (MAC) operations provide opportunities to significantly improve energy efficiency and throughput of DNN accelerators wi…

cs.DC2020★ 14 cited

ZigZag: A Memory-Centric Rapid DNN Accelerator Design Space Exploration Framework

Linyan Mei, Pouya Houshmand, Vikram Jain +2

Building efficient embedded deep learning systems requires a tight co-design between DNN algorithms, memory hierarchy, and dataflow. However, owing to the large degrees of freedom…