47 citations · 92 across the 7 of their papers we have counts for
5 papers · 1 filter
SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
Victor J. B. Jung, Arne Symons, Linyan Mei +2
To meet the growing need for computational power for DNNs, multiple specialized hardware architectures have been proposed. Each DNN layer should be mapped onto the hardware with th…
TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge
Vikram Jain, Sebastian Giraldo, Jaro De Roose +3
Extreme edge devices or Internet-of-thing nodes require both ultra-low power always-on processing as well as the ability to do on-demand sampling and processing. Moreover, support…
Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators
Arne Symons, Linyan Mei, Steven Colleman +3
As the landscape of deep neural networks evolves, heterogeneous dataflow accelerators, in the form of multi-core architectures or chiplet-based designs, promise more flexibility an…
DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling
Linyan Mei, Koen Goetschalckx, Arne Symons +1
DNN workloads can be scheduled onto DNN accelerators in many different ways: from layer-by-layer scheduling to cross-layer depth-first scheduling (a.k.a. layer fusion, or cascaded…
CONVOLVE: Smart and seamless design of smart edge processors
M. Gomony, F. Putter, A. Gebregiorgis +25
With the rise of Deep Learning (DL), our world braces for AI in every edge device, creating an urgent need for edge-AI SoCs. This SoC hardware needs to support high throughput, rel…