activity
20192023
most citedSMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations

81 citations · 98 across the 7 of their papers we have counts for

collaborators

8 papers

cs.AR2023

Swordfish: A Framework for Evaluating Deep Neural Network-based Basecalling using Computation-In-Memory with Non-Ideal Memristors

Taha Shahroodi, Gagandeep Singh, Mahdi Zahedi +6

Basecalling, an essential step in many genome analysis studies, relies on large Deep Neural Networks (DNNs) to achieve high accuracy. Unfortunately, these DNNs are computationally…

cs.ET2022

BCIM: Efficient Implementation of Binary Neural Network Based on Computation in Memory

Mahdi Zahedi, Taha Shahroodi, Stephan Wong +1

Applications of Binary Neural Networks (BNNs) are promising for embedded systems with hard constraints on computing power. Contrary to conventional neural networks with the floatin…

cs.AR20226 cited

A Case for Transparent Reliability in DRAM Systems

Minesh Patel, Taha Shahroodi, Aditya Manglik +4

Today's systems have diverse needs that are difficult to address using one-size-fits-all commodity DRAM. Unfortunately, although system designers can theoretically adapt commodity…

cs.AR2021

BurstLink: Techniques for Energy-Efficient Conventional and Virtual Reality Video Display

Jawad Haj-Yahya, Jisung Park, Rahul Bera +5

Conventional planar video streaming is the most popular application in mobile systems and the rapid growth of 360 video content and virtual reality (VR) devices are accelerating th…

cs.AR20201 cited

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Minesh Patel, Jeremie S. Kim, Taha Shahroodi +2

Increasing single-cell DRAM error rates have pushed DRAM manufacturers to adopt on-die error-correction coding (ECC), which operates entirely within a DRAM chip to improve factory…

cs.AR20209 cited

CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off

Haocong Luo, Taha Shahroodi, Hasan Hassan +5

DRAM is the prevalent main memory technology, but its long access latency can limit the performance of many workloads. Although prior works provide DRAM designs that reduce DRAM ac…