47 citations · 58 across the 9 of their papers we have counts for
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cs.AR2007
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
P. Bernardi, G. Masera, F. Quaglio +1
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-a-chip (SoC) environments. The approach advantages are the ab…
cs.AR2007★ 2 cited
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
F. Lima Kastensmidt, L. Sterpone, L. Carro +1
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by…