31 citations · 34 across the 3 of their papers we have counts for
3 papers
cs.AR2020★ 31 cited
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
Zhe Lin, Jieru Zhao, Sharad Sinha +1
High-level synthesis (HLS) enables designers to customize hardware designs efficiently. However, it is still challenging to foresee the correlation between power consumption and HL…
cs.CV2020★ 2 cited
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
Jieru Zhao, Tingyuan Liang, Liang Feng +4
Fast and accurate depth estimation, or stereo matching, is essential in embedded stereo vision systems, requiring substantial design effort to achieve an appropriate balance among…
cs.DC2019★ 1 cited
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
Jieru Zhao, Tingyuan Liang, Sharad Sinha +1
High-level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction level. Optimization of complex appl…