31 citations · 37 across the 12 of their papers we have counts for
12 papers
StrataCL: Fabric-Native Communication Library for Production Supernodes
Tiancheng Hu, Jin Qin, Yuzheng Wang +14
Modern distributed AI workloads run across hundreds of accelerators, making communication a major bottleneck. Existing communication libraries remain largely buffer-centric because…
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
Mingzhe Gao, Jieru Zhao, Zhe Lin +1
High-level synthesis (HLS) notably speeds up the hardware design process by avoiding RTL programming. However, the turnaround time of HLS increases significantly when post-route qu…
An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
Weichuang Zhang, Jieru Zhao, Guan Shen +3
With the increasing demand for computing capability given limited resource and power budgets, it is crucial to deploy applications to customized accelerators like FPGAs. However, F…
MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems
Guan Shen, Jieru Zhao, Zeke Wang +5
Along with the fast evolution of deep neural networks, the hardware system is also developing rapidly. As a promising solution achieving high scalability and low manufacturing cost…
FlowMap: Path Generation for Automated Vehicles in Open Space Using Traffic Flow
Wenchao Ding, Jieru Zhao, Yubin Chu +5
There is extensive literature on perceiving road structures by fusing various sensor inputs such as lidar point clouds and camera images using deep neural nets. Leveraging the late…
DataFlower: Exploiting the Data-flow Paradigm for Serverless Workflow Orchestration
Zijun Li, Chuhao Xu, Quan Chen +3
Serverless computing that runs functions with auto-scaling is a popular task execution pattern in the cloud-native era. By connecting serverless functions into workflows, tenants c…
AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA
Tingyuan Liang, Gengjie Chen, Jieru Zhao +2
On modern field-programmable gate arrays (FPGAs), certain critical path portions of the designs might be prearranged into many multi-cell macros during synthesis. These movable mac…
SALO: An Efficient Spatial Accelerator Enabling Hybrid Sparse Attention Mechanisms for Long Sequences
Guan Shen, Jieru Zhao, Quan Chen +3
The attention mechanisms of transformers effectively extract pertinent information from the input sequence. However, the quadratic complexity of self-attention w.r.t the sequence l…
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
Zhe Lin, Zike Yuan, Jieru Zhao +3
Power estimation is the basis of many hardware optimization strategies. However, it is still challenging to offer accurate power estimation at an early stage such as high-level syn…
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
Zhe Lin, Jieru Zhao, Sharad Sinha +1
High-level synthesis (HLS) enables designers to customize hardware designs efficiently. However, it is still challenging to foresee the correlation between power consumption and HL…
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
Jieru Zhao, Tingyuan Liang, Liang Feng +4
Fast and accurate depth estimation, or stereo matching, is essential in embedded stereo vision systems, requiring substantial design effort to achieve an appropriate balance among…
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
Jieru Zhao, Tingyuan Liang, Sharad Sinha +1
High-level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction level. Optimization of complex appl…