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cs.AR2024
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
Mingzhe Gao, Jieru Zhao, Zhe Lin +1
High-level synthesis (HLS) notably speeds up the hardware design process by avoiding RTL programming. However, the turnaround time of HLS increases significantly when post-route qu…
cs.AR2024
An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
Weichuang Zhang, Jieru Zhao, Guan Shen +3
With the increasing demand for computing capability given limited resource and power budgets, it is crucial to deploy applications to customized accelerators like FPGAs. However, F…