31 citations · 37 across the 12 of their papers we have counts for
5 papers · 1 filter
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
Mingzhe Gao, Jieru Zhao, Zhe Lin +1
High-level synthesis (HLS) notably speeds up the hardware design process by avoiding RTL programming. However, the turnaround time of HLS increases significantly when post-route qu…
An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
Weichuang Zhang, Jieru Zhao, Guan Shen +3
With the increasing demand for computing capability given limited resource and power budgets, it is crucial to deploy applications to customized accelerators like FPGAs. However, F…
AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA
Tingyuan Liang, Gengjie Chen, Jieru Zhao +2
On modern field-programmable gate arrays (FPGAs), certain critical path portions of the designs might be prearranged into many multi-cell macros during synthesis. These movable mac…
SALO: An Efficient Spatial Accelerator Enabling Hybrid Sparse Attention Mechanisms for Long Sequences
Guan Shen, Jieru Zhao, Quan Chen +3
The attention mechanisms of transformers effectively extract pertinent information from the input sequence. However, the quadratic complexity of self-attention w.r.t the sequence l…
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
Zhe Lin, Jieru Zhao, Sharad Sinha +1
High-level synthesis (HLS) enables designers to customize hardware designs efficiently. However, it is still challenging to foresee the correlation between power consumption and HL…