192 citations · 730 across the 29 of their papers we have counts for
6 papers · 1 filter
Thales: Formulating and Estimating Architectural Vulnerability Factors for DNN Accelerators
Abhishek Tyagi, Yiming Gan, Shaoshan Liu +3
As Deep Neural Networks (DNNs) are increasingly deployed in safety critical and privacy sensitive applications such as autonomous driving and biometric authentication, it is critic…
AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator
Chuteng Zhou, Fernando Garcia Redondo, Julian Büchel +7
Always-on TinyML perception tasks in IoT applications require very high energy efficiency. Analog compute-in-memory (CiM) using non-volatile memory (NVM) promises high efficiency a…
S2TA: Exploiting Structured Sparsity for Energy-Efficient Mobile CNN Acceleration
Zhi-Gang Liu, Paul N. Whatmough, Yuhao Zhu +1
Exploiting sparsity is a key technique in accelerating quantized convolutional neural network (CNN) inference on mobile devices. Prior sparse CNN accelerators largely exploit un-st…
EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference
Thierry Tambe, Coleman Hooper, Lillian Pentecost +8
Transformer-based language models such as BERT provide significant accuracy improvement for a multitude of natural language processing (NLP) tasks. However, their hefty computation…
Sparse Systolic Tensor Array for Efficient CNN Hardware Acceleration
Zhi-Gang Liu, Paul N. Whatmough, Matthew Mattina
Convolutional neural network (CNN) inference on mobile devices demands efficient hardware acceleration of low-precision (INT8) general matrix multiplication (GEMM). Exploiting data…
CHIPKIT: An agile, reusable open-source framework for rapid test chip development
Paul Whatmough, Marco Donato, Glenn Ko +3
The current trend for domain-specific architectures (DSAs) has led to renewed interest in research test chips to demonstrate new specialized hardware. Tape-outs also offer huge ped…