SCALE-Sim: Systolic CNN Accelerator Simulator

Abstract

Systolic Arrays are one of the most popular compute substrates within Deep Learning accelerators today, as they provide extremely high efficiency for running dense matrix multiplications. However, the research community lacks tools to insights on both the design trade-offs and efficient mapping strategies for systolic-array based accelerators. We introduce Systolic CNN Accelerator Simulator (SCALE-Sim), which is a configurable systolic array based cycle accurate DNN accelerator simulator. SCALE-Sim exposes various micro-architectural features as well as system integration parameters to the designer to enable comprehensive design space exploration. This is the first systolic-array simulator tuned for running DNNs to the best of our knowledge. Using SCALE-Sim, we conduct a suite of case studies and demonstrate the effect of bandwidth, data flow and aspect ratio on the overall runtime and energy of Deep Learning kernels across vision, speech, text, and games. We believe that these insights will be highly beneficial to architects and ML practitioners.

References in corpus (4)

• Faster R-CNN: Towards Real-Time Object Detection with Region Proposal Networks
• Deep Speech 2: End-to-End Speech Recognition in English and Mandarin
• Effective Use of Word Order for Text Categorization with Convolutional Neural Networks
• A Survey of Deep Network Solutions for Learning Control in Robotics: From Reinforcement to Imitation

Cited by in corpus (20)

• Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead
• ARK: Fully Homomorphic Encryption Accelerator with Runtime Data Generation and Inter-Operation Key Reuse
• Recurrent Neural Networks: An Embedded Computing Perspective
• Mind Mappings: Enabling Efficient Algorithm-Accelerator Mapping Space Search
• ASTRA-sim2.0: Modeling Hierarchical Networks and Disaggregated Systems for Large-model Training at Scale
• FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
• Control Variate Approximation for DNN Accelerators
• SMART: A Heterogeneous Scratchpad Memory Architecture for Superconductor SFQ-based Systolic CNN Accelerators
• DaCapo: Accelerating Continuous Learning in Autonomous Systems for Video Analytics
• LayerPipe: Accelerating Deep Neural Network Training by Intra-Layer and Inter-Layer Gradient Pipelining and Multiprocessor Scheduling
• HarDNet: A Low Memory Traffic Network
• FlexSA: Flexible Systolic Array Architecture for Efficient Pruned DNN Model Training
• A Gradient-Interleaved Scheduler for Energy-Efficient Backpropagation for Training Neural Networks
• Energy-Efficient Accelerator Design for Deformable Convolution Networks
• AutoPilot: Automating SoC Design Space Exploration for SWaP Constrained Autonomous UAVs
• DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architectures
• AIRCHITECT: Learning Custom Architecture Design and Mapping Space
• Energy Predictive Models for Convolutional Neural Networks on Mobile Platforms
• Rapid Model Architecture Adaption for Meta-Learning
• GrateTile: Efficient Sparse Tensor Tiling for CNN Processing