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20192023
most citedHybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Prediction

3 citations · 10 across the 14 of their papers we have counts for

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Showing 2023Show all

7 papers · 1 filter

cs.CR2023★ 2 cited

CoPriv: Network/Protocol Co-Optimization for Communication-Efficient Private Inference

Wenxuan Zeng, Meng Li, Haichuan Yang +3

Deep neural network (DNN) inference based on secure 2-party computation (2PC) can offer cryptographically-secure privacy protection but suffers from orders of magnitude latency ove…

cs.AR2023

Post-Layout Simulation Driven Analog Circuit Sizing

Xiaohan Gao, Haoyi Zhang, Siyuan Ye +6

Post-layout simulation provides accurate guidance for analog circuit design, but post-layout performance is hard to be directly optimized at early design stages. Prior work on anal…

cs.AR2023

READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction

Zuodong Zhang, Renjie Wei, Meng Li +3

With the rapid advancements of deep learning in recent years, hardware accelerators are continuously deployed in more and more safety-critical applications such as autonomous drivi…

cs.CR2023

Falcon: Accelerating Homomorphically Encrypted Convolutions for Efficient Private Mobile Network Inference

Tianshi Xu, Meng Li, Runsheng Wang +1

Efficient networks, e.g., MobileNetV2, EfficientNet, etc, achieves state-of-the-art (SOTA) accuracy with lightweight computation. However, existing homomorphic encryption (HE)-base…

physics.app-ph2023

The interface states in gate-all-around transistors (GAAFETs)

Yue-Yang Liu, Haoran Lu, Zirui Wang +5

The atomic-level structural detail and the quantum effects are becoming crucial to device performance as the emerging advanced transistors, representatively GAAFETs, are scaling do…

cs.LG2023★ 3 cited

HybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Prediction

Yuxiang Zhao, Zhuomin Chai, Yibo Lin +2

Accurate early congestion prediction can prevent unpleasant surprises at the routing stage, playing a crucial character in assisting designers to iterate faster in VLSI design cycl…