activity
20142025
most citedDSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks

38 citations · 106 across the 12 of their papers we have counts for

collaborators

14 papers

cs.LG2025

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs

Muhammad Sabih, Abrarul Karim, Jakob Wittmann +2

The customizability of RISC-V makes it an attractive choice for accelerating deep neural networks (DNNs). It can be achieved through instruction set extensions and corresponding cu…

cs.AR2025

Evaluation of CGRA Toolchains

Dominik Walter, Marita Halm, Daniel Seidel +4

Increasing demands for computing power also propel the need for energy-efficient SoC accelerator architectures. One class for such accelerators are so-called processor arrays, whic…

cs.AR2025

Mapping and Execution of Nested Loops on Processor Arrays: CGRAs vs. TCPAs

Dominik Walter, Marita Halm, Daniel Seidel +4

Increasing demands for computing power also propel the need for energy-efficient SoC accelerator architectures. One class of such accelerators are so-called processor arrays, which…

cs.CV2024★ 2 cited

microYOLO: Towards Single-Shot Object Detection on Microcontrollers

Mark Deutel, Christopher Mutschler, Jürgen Teich

This work-in-progress paper presents results on the feasibility of single-shot object detection on microcontrollers using YOLO. Single-shot object detectors like YOLO are widely us…

cs.LG2024★ 17 cited

On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers

Mark Deutel, Frank Hannig, Christopher Mutschler +1

On-device training of DNNs allows models to adapt and fine-tune to newly collected data or changing domains while deployed on microcontroller units (MCUs). However, DNN training is…

cs.AR2023★ 3 cited

To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations

Patrick Plagwitz, Frank Hannig, Jürgen Teich +1

Convolutional Neural Networks (CNNs) are widely employed to solve various problems, e.g., image classification. Due to their compute- and data-intensive nature, CNN accelerators ha…

cs.LG2023★ 6 cited

Combining Multi-Objective Bayesian Optimization with Reinforcement Learning for TinyML

Mark Deutel, Georgios Kontes, Christopher Mutschler +1

Deploying deep neural networks (DNNs) on microcontrollers (TinyML) is a common trend to process the increasing amount of sensor data generated at the edge, but in practice, resourc…

cs.AR2022★ 34 cited

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks

Jan Sommer, M. Akif Özkan, Oliver Keszocze +1

Spiking Neural Networks (SNNs) compute in an event-based matter to achieve a more efficient computation than standard Neural Networks. In SNNs, neuronal outputs (i.e. activations)…

cs.AR2022★ 38 cited

DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks

Jan Sommer, M. Akif Özkan, Oliver Keszocze +1

The number of Digital Signal Processor (DSP) resources available in Field Programmable Gate Arrays (FPGAs) is often quite limited. Therefore, full utilization of available DSP reso…

cs.DC2021

Symbolic Loop Compilation for Tightly Coupled Processor Arrays

Michael Witterauf, Dominik Walter, Frank Hannig +1

Loop compilation for Tightly Coupled Processor Arrays (TCPAs), a class of massively parallel loop accelerators, entails solving NP-hard problems, yet depends on the loop bounds and…

cs.CV2020★ 4 cited

HipaccVX: Wedding of OpenVX and DSL-based Code Generation

M. Akif Özkan, Burak Ok, Bo Qiao +2

Writing programs for heterogeneous platforms optimized for high performance is hard since this requires the code to be tuned at a low level with architecture-specific optimizations…

cs.DS2019★ 2 cited

Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice

Bertrand Simon, Joachim Falk, Nicole Megow +1

Static (offline) techniques for mapping applications given by task graphs to MPSoC systems often deliver overly pessimistic and thus suboptimal results w.r.t. exploiting time slack…

cs.NI2019

Adaptive Predictive Power Management for Mobile LTE Devices

Peter Brand, Joachim Falk, Jonathan Ah Sue +3

Reducing the energy consumption of mobile phones is a crucial design goal for cellular modem solutions for LTE and 5G standards. In addition to improving the power efficiency of co…

cs.MS2014

A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms

Harald Koestler, Christian Schmitt, Sebastian Kuckuk +3

Many problems in computational science and engineering involve partial differential equations and thus require the numerical solution of large, sparse (non)linear systems of equati…