LSQCA: Resource-Efficient Load/Store Architecture for Limited-Scale Fault-Tolerant Quantum Computing
arXiv:2412.20486 · doi:10.1109/HPCA61900.2025.00033
Abstract
Current fault-tolerant quantum computer (FTQC) architectures utilize several encoding techniques to enable reliable logical operations with restricted qubit connectivity. However, such logical operations demand additional memory overhead to ensure fault tolerance. Since the main obstacle to practical quantum computing is the limited qubit count, our primary mission is to design floorplans that can reduce memory overhead without compromising computational capability. Despite extensive efforts to explore FTQC architectures, even the current state-of-the-art floorplan strategy devotes 50% of memory space to this overhead, not to data storage, to ensure unit-time random access to all logical qubits. In this paper, we propose an FTQC architecture based on a novel floorplan strategy, Load/Store Quantum Computer Architecture (LSQCA), which can achieve almost 100% memory density. The idea behind our architecture is to separate all memory regions into small computational space called Computational Registers (CR) and space-efficient memory space called Scan-Access Memory (SAM). We define an instruction set for these abstract structures and provide concrete designs named point-SAM and line-SAM architectures. With this design, we can improve the memory density by allowing variable-latency memory access while concealing the latency with other bottlenecks. We also propose optimization techniques to exploit properties of quantum programs observed in our static analysis, such as access locality in memory reference timestamps. Our numerical results indicate that LSQCA successfully leverages this idea. In a resource-restricted situation, a specific benchmark shows that we can achieve about 90% memory density with 5% increase in the execution time compared to a conventional floorplan, which achieves at most 50% memory density for unit-time random access. Our design ensures broad quantum applicability.
17 pages, 15 figures, 2025 IEEE International Symposium on High Performance Computer Architecture (HPCA)
References in corpus (21)
- Quantum algorithm for solving linear systems of equations
- Surface codes: Towards practical large-scale quantum computation
- Suppressing quantum errors by scaling a surface code logical qubit
- Logical quantum processor based on reconfigurable atom arrays
- High-threshold and low-overhead fault-tolerant quantum memory
- Real-time quantum error correction beyond break-even
- Magic state distillation with low overhead
- Even more efficient quantum computations of chemistry through tensor hypercontraction
- Blueprint for a Scalable Photonic Fault-Tolerant Quantum Computer
- Building a fault-tolerant quantum computer using concatenated cat codes
- Heisenberg-limited ground state energy estimation for early fault-tolerant quantum computers
- Optimal Resources for Topological 2D Stabilizer Codes: Comparative Study
- Focus beyond quadratic speedups for error-corrected quantum advantage
- Reliably assessing the electronic structure of cytochrome P450 on today's classical computers and tomorrow's quantum computers
- Universal quantum computing with twist-free and temporally encoded lattice surgery
- Surface code compilation via edge-disjoint paths
- Hunting for quantum-classical crossover in condensed matter problems
- Partially Fault-tolerant Quantum Computing Architecture with Error-corrected Clifford Gates and Space-time Efficient Analog Rotations
- Looped Pipelines Enabling Effective 3D Qubit Lattices in a Strictly 2D Device
- Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays
- Resource Optimized Quantum Architectures for Surface Code Implementations of Magic-State Distillation