Experimental demonstration of an integrated on-chip p-bit core utilizing stochastic Magnetic Tunnel Junctions and 2D-MoS2 FETs

Abstract

Probabilistic computing is a novel computing scheme that offers a more efficient approach than conventional CMOS-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic-bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic Magnetic Tunnel Junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, through integrating stochastic MTJs with 2D-MoS${}_2$ FETs, the first on-chip realization of a key p-bit building block displaying voltage-controllable stochasticity is demonstrated. In addition, supported by circuit simulations, this work provides a careful analysis of the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. This understanding of the interplay between the characteristics of the transistors and the MTJ is vital for the construction of a fully functioning p-bit, making the design rules presented in this article key for future experimental implementations of scaled on-chip p-bit networks.

References in corpus (22)

• High Current Density in Monolayer MoS${}_2$ Doped by AlO${}_x$
• p-Bits for Probabilistic Spin Logic
• Massively Parallel Probabilistic Computing with Sparse Ising Machines
• Low-Energy Truly Random Number Generation with Superparamagnetic Tunnel Junctions for Unconventional Computing
• The promise of spintronics for unconventional computing
• A full-stack view of probabilistic computing with p-bits: devices, architectures and algorithms
• Demonstration of nanosecond operation in stochastic magnetic tunnel junctions
• Probabilistic computing with p-bits
• Hardware emulation of stochastic p-bits for invertible logic
• Hardware-aware $insitu$ Boltzmann machine learning using stochastic magnetic tunnel junctions
• Low Barrier Nanomagnets as p-bits for Spin Logic
• CMOS + stochastic nanomagnets: heterogeneous computers for probabilistic inference and learning
• Weighted p-bits for FPGA implementation of probabilistic circuits
• Implementing Bayesian Networks with Embedded Stochastic MRAM
• Low Barrier Magnet Design for Efficient Hardware Binary Stochastic Neurons
• Autonomous Probabilistic Coprocessing with Petaflips per Second
• Experimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions
• Quantitative Evaluation of Hardware Binary Stochastic Neurons
• Double Free-Layer Magnetic Tunnel Junctions for Probabilistic Bits
• Accelerated Quantum Monte Carlo with Probabilistic Computers
• Correlated fluctuations in spin orbit torque-coupled perpendicular nanomagnets
• Hardware Design for Autonomous Bayesian Networks

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• CMOS + stochastic nanomagnets: heterogeneous computers for probabilistic inference and learning
• GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling
• The First Hardware Demonstration of a Universal Programmable RRAM-based Probabilistic Computer for Molecular Docking
• Sub-universal variational circuits for combinatorial optimization problems
• Improving deep neural network performance through sampling