Weighted p-bits for FPGA implementation of probabilistic circuits

Abstract

Probabilistic spin logic (PSL) is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits (p-bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve problems of optimization, inference and also to implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this paper we present a scalable FPGA implementation of such invertible p-circuits. We implement a "weighted" p-bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p-bits to which a large class of problems beyond invertible Boolean logic can be mapped, and how invertibility can be applied to interesting problems such as the NP-complete Subset Sum Problem by solving a small instance of this problem in hardware.

References in corpus (9)

• Stochastic p-bits for Invertible Logic
• Minor-embedding in adiabatic quantum computation: II. Minor-universal graph design
• Intrinsic optimization using stochastic nanomagnets
• Non-perturbative k-body to two-body commuting conversion Hamiltonians and embedding problem instances into Ising spins
• Hardware emulation of stochastic p-bits for invertible logic
• Low Barrier Nanomagnets as p-bits for Spin Logic
• Simulating spin systems on IANUS, an FPGA-based computer
• A building block for hardware belief networks
• Oscillator-based Ising Machine

Cited by in corpus (19)

• p-Bits for Probabilistic Spin Logic
• Hardware-aware $insitu$ Boltzmann machine learning using stochastic magnetic tunnel junctions
• Implementing Bayesian Networks with Embedded Stochastic MRAM
• Efficient CMOS Invertible Logic Using Stochastic Computing
• Biasing the quantum vacuum to control macroscopic probability distributions
• Experimental demonstration of an integrated on-chip p-bit core utilizing stochastic Magnetic Tunnel Junctions and 2D-MoS2 FETs
• Hardware Design for Autonomous Bayesian Networks
• Probabilistic-Bits based on Ferroelectric Field-Effect Transistors for Stochastic Computing
• Enhanced Convergence in p-bit Based Simulated Annealing with Partial Deactivation for Large-Scale Combinatorial Optimization Problems
• Physics-inspired Ising Computing with Ring Oscillator Activated p-bits
• Noise-augmented Chaotic Ising Machines for Combinatorial Optimization and Sampling
• Nonvolatile bistable memory and Ising machine based on Micro-Electro-Mechanical Systems
• High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians
• GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling
• pc-COP: An Efficient and Configurable 2048-p-Bit Fully-Connected Probabilistic Computing Accelerator for Combinatorial Optimization
• The First Hardware Demonstration of a Universal Programmable RRAM-based Probabilistic Computer for Molecular Docking
• Ground-State Probabilistic Logic with the Simplest Binary Energy Landscape for Probabilistic Computing
• An improved update rule for probabilistic computers
• Improving deep neural network performance through sampling