CMOS back-end-of-line compatible ferroelectric tunnel junction devices

Veeresh Deshpande; Keerthana Shajil Nair; Marco Holzer; Sourish Banerjee; Catherine Dubourdieu

doi:10.1016/j.sse.2021.108054

paper

CMOS back-end-of-line compatible ferroelectric tunnel junction devices

arXiv:2108.10941 · doi:10.1016/j.sse.2021.108054

Abstract

Ferroelectric tunnel junction devices based on ferroelectric thin films of solid solutions of hafnium dioxide can enable CMOS integration of ultra-low power ferroelectric devices with potential for memory and emerging computing schemes such as in-memory computing and neuromorphic applications. In this work, we present ferroelectric tunnel junctions based on Hf $_{0.5}$ Zr $_{0.5}$ O $_{2}$ with materials and processes compatible with CMOS back-end-of-line integration. We show a device architecture based on W-Hf $_{0.5}$ Zr $_{0.5}$ O $_{2}$ -Al $_{2}$ O $_{3}$ -TiN stacks featuring low temperature annealing at 400°C with performance comparable to those obtained with higher temperature annealing conditions.