Agile SoC Development with Open ESP
arXiv:2009.01178 · doi:10.1145/3400302.3415753
Abstract
ESP is an open-source research platform for heterogeneous SoC design. The platform combines a modular tile-based architecture with a variety of application-oriented flows for the design and optimization of accelerators. The ESP architecture is highly scalable and strikes a balance between regularity and specialization. The companion methodology raises the level of abstraction to system-level design and enables an automated flow from software and hardware development to full-system prototyping on FPGA. For application developers, ESP offers domain-specific automated solutions to synthesize new accelerators for their software and to map complex workloads onto the SoC architecture. For hardware engineers, ESP offers automated solutions to integrate their accelerator designs into the complete SoC. Conceived as a heterogeneous integration platform and tested through years of teaching at Columbia University, ESP supports the open-source hardware community by providing a flexible platform for agile SoC development.
Invited Paper at the 2020 International Conference On Computer Aided Design (ICCAD) - Special Session on Opensource Tools and Platforms for Agile Development of Specialized Architectures
References in corpus (4)
- Fast inference of deep neural networks in FPGAs for particle physics
- The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology
- COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators
- HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA
Cited by in corpus (9)
- ShEF: Shielded Enclaves for Cloud FPGAs
- CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs
- CEDR -- A Compiler-integrated, Extensible DSSoC Runtime
- Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs
- From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics
- An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
- EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms
- Compiler Infrastructure for Specializing Domain-Specific Memory Templates
- Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems