95 citations · 286 across the 14 of their papers we have counts for
15 papers
Neural network accelerator for quantum control
David Xu, A. Barış Özgüler, Giuseppe Di Guglielmo +4
Efficient quantum control is necessary for practical quantum computing implementations with current technologies. Conventional algorithms for determining optimal control parameters…
Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP
Joseph Zuckerman, Paolo Mantovani, Davide Giri +1
Heterogeneous, multicore SoC architectures are a critical component of today's computing landscape. However, supporting both increasing heterogeneity and multicore execution are si…
Real-time Inference with 2D Convolutional Neural Networks on Field Programmable Gate Arrays for High-rate Particle Imaging Detectors
Yeon-jae Jwa, Giuseppe Di Guglielmo, Lukas Arnold +2
We present a custom implementation of a 2D Convolutional Neural Network (CNN) as a viable application for real-time data selection in high-resolution and high-rate particle imaging…
Accelerating Deep Neural Networks for Real-time Data Selection for High-resolution Imaging Particle Detectors
Yeon-Jae Jwa, Giuseppe Di Guglielmo, Luca P. Carloni +1
This paper presents the custom implementation, optimization, and performance evaluation of convolutional neural networks on field programmable gate arrays, for the purposes of acce…
Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs
Joseph Zuckerman, Davide Giri, Jihye Kwon +2
One of the most critical aspects of integrating loosely-coupled accelerators in heterogeneous SoC architectures is orchestrating their interactions with the memory hierarchy, espec…
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition
Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni +12
Hardware accelerators (HAs) are essential building blocks for fast and energy-efficient computing systems. Accelerator Quick Error Detection (A-QED) is a recent formal technique wh…
hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices
Farah Fahim, Benjamin Hawks, Christian Herwig +27
Accessible machine learning algorithms, software, and diagnostic tools for energy-efficient devices and systems are extremely valuable across a broad range of application domains.…
DB4HLS: A Database of High-Level Synthesis Design Space Explorations
Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni +3
High-Level Synthesis (HLS) frameworks allow to easily specify a large number of variants of the same hardware design by only acting on optimization directives. Nonetheless, the har…
Agile SoC Development with Open ESP
Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo +6
ESP is an open-source research platform for heterogeneous SoC design. The platform combines a modular tile-based architecture with a variety of application-oriented flows for the d…
CRYLOGGER: Detecting Crypto Misuses Dynamically
Luca Piccolboni, Giuseppe Di Guglielmo, Luca P. Carloni +1
Cryptographic (crypto) algorithms are the essential ingredients of all secure systems: crypto hash functions and encryption algorithms, for example, can guarantee properties such a…
The MosaicSim Simulator (Full Technical Report)
Opeoluwa Matthews, Aninda Manocha, Davide Giri +7
As Moore's Law has slowed and Dennard Scaling has ended, architects are increasingly turning to heterogeneous parallelism and domain-specific hardware-software co-designs. These tr…
ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning
Davide Giri, Kuan-Lin Chiu, Giuseppe Di Guglielmo +2
We present ESP4ML, an open-source system-level design flow to build and program SoC architectures for embedded applications that require the hardware acceleration of machine learni…
PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators
Luca Piccolboni, Giuseppe Di Guglielmo, Luca P. Carloni
Software-based attacks exploit bugs or vulnerabilities to get unauthorized access or leak confidential information. Dynamic information flow tracking (DIFT) is a security technique…
COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators
Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo +1
Hardware accelerators are key to the efficiency and performance of system-on-chip (SoC) architectures. With high-level synthesis (HLS), designers can easily obtain several performa…
Securing Accelerators with Dynamic Information Flow Tracking
Luca Piccolboni, Giuseppe Di Guglielmo, Luca Carloni
Systems-on-chip (SoCs) are becoming heterogeneous: they combine general-purpose processor cores with application-specific hardware components, also known as accelerators, to improv…