CEDR -- A Compiler-integrated, Extensible DSSoC Runtime
arXiv:2204.08962 · doi:10.1145/3529257
Abstract
In this work, we present CEDR, a Compiler-integrated, Extensible Domain Specific System on Chip Runtime ecosystem to facilitate research towards addressing the challenges of architecture, system software and application development with distinct plug-and-play integration points in a unified compile time and run time workflow. We demonstrate the utility of CEDR on the Xilinx Zynq MPSoC-ZCU102 for evaluating performance of pre-silicon hardware in the trade space of SoC configuration, scheduling policy and workload complexity based on dynamically arriving workload scenarios composed of real-life signal processing applications scaling to thousands of application instances with FFT and matrix multiply accelerators. We provide insights into the trade-offs present in this design space through a number of distinct case studies. CEDR is portable and has been deployed and validated on Odroid-XU3, X86 and Nvidia Jetson Xavier based SoC platforms. Taken together, CEDR is a capable environment for enabling research in exploring the boundaries of productive application development, resource management heuristic development, and hardware configuration analysis for heterogeneous architectures.
arXiv comment35 pages single column, 16 figures, 7 tables. Accepted for publication in the ACM Transactions on Embedded and Computing Systems
References in corpus (6)
- Agile SoC Development with Open ESP
- Runtime Task Scheduling using Imitation Learning for Heterogeneous Many-Core Systems
- Scheduling Beyond CPUs for HPC
- PRUNE: Dynamic and Decidable Dataflow for Signal Processing on Heterogeneous Platforms
- DAS: Dynamic Adaptive Scheduling for Energy-Efficient Heterogeneous SoCs
- ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures