Experimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions

Abstract

The recently proposed probabilistic spin logic presents promising solutions to novel computing applications. Multiple cases of implementations, including invertible logic gate, have been studied numerically by simulations. Here we report an experimental demonstration of a magnetic tunnel junction-based hardware implementation of probabilistic spin logic.

arXiv comment4 pages, 17 figures

References in corpus (4)

• Stochastic p-bits for Invertible Logic
• Implementing Bayesian Networks with Embedded Stochastic MRAM
• Experimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions
• Robustness and scalability of p-bits implemented with low energy barrier nanomagnets

Cited by in corpus (12)

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• A full-stack view of probabilistic computing with p-bits: devices, architectures and algorithms
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• Hardware-aware $insitu$ Boltzmann machine learning using stochastic magnetic tunnel junctions
• Autonomous Probabilistic Coprocessing with Petaflips per Second
• Experimental demonstration of an integrated on-chip p-bit core utilizing stochastic Magnetic Tunnel Junctions and 2D-MoS2 FETs
• Experimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions
• Voltage-insensitive stochastic magnetic tunnel junctions with double free layers
• The Strong Sensitivity of the Characteristics of Binary Stochastic Neurons Employing Low Barrier Nanomagnets to Small Geometrical Variations
• Sub-Nanosecond Spin-Transfer Torque in an Ensemble of Superparamagnetic-Like Nanomagnets
• Measurement-driven neural-network training for integrated magnetic tunnel junction arrays
• Metrics for spin-based computing