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20162023
most citedInferring Fine-grained Control Flow Inside SGX Enclaves with Branch Shadowing

232 citations · 411 across the 23 of their papers we have counts for

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Showing cs.ARShow all

8 papers · 1 filter

cs.AR2023★ 3 cited

RV-CURE: A RISC-V Capability Architecture for Full Memory Safety

Yonghae Kim, Anurag Kar, Jaewon Lee +2

Despite decades of efforts to resolve, memory safety violations are still persistent and problematic in modern systems. Various defense mechanisms have been proposed, but their dep…

cs.AR2023★ 1 cited

VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs

Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya +5

Deep Learning (DL) acceleration support in CPUs has recently gained a lot of traction, with several companies (Arm, Intel, IBM) announcing products with specialized matrix engines…

cs.AR2021

Vortex: Extending the RISC-V ISA for GPGPU and 3D-GraphicsResearch

Blaise Tine, Fares Elsabbagh, Krishna Yalamarthy +1

The importance of open-source hardware and software has been increasing. However, despite GPUs being one of the more popular accelerators across various applications, there is very…

cs.AR2021

RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU

Geonhwa Jeong, Eric Qin, Ananda Samajdar +4

As AI-based applications become pervasive, CPU vendors are starting to incorporate matrix engines within the datapath to boost efficiency. Systolic arrays have been the premier arc…

cs.AR2020★ 15 cited

Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads

Bahar Asgari, Ramyad Hadidi, Joshua Dierberger +3

Sparse matrices are the key ingredients of several application domains, from scientific computation to machine learning. The primary challenge with sparse matrices has been efficie…

cs.AR2017

Louvre: Lightweight Ordering Using Versioning for Release Consistency

Pranith Kumar, Prasun Gera, Hyojong Kim +1

Fence instructions are fundamental primitives that ensure consistency in a weakly consistent shared memory multi-core processor. The execution cost of these instructions is signifi…

cs.AR2017★ 21 cited

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube

Ramyad Hadidi, Bahar Asgari, Jeffrey Young +4

Memories that exploit three-dimensional (3D)-stacking technology, which integrate memory and logic dies in a single stack, are becoming popular. These memories, such as Hybrid Memo…

cs.AR2017★ 64 cited

Demystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube

Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar +3

Three-dimensional (3D)-stacking technology, which enables the integration of DRAM and logic dies, offers high bandwidth and low energy consumption. This technology also empowers ne…