232 citations · 411 across the 23 of their papers we have counts for
23 papers
RV-CURE: A RISC-V Capability Architecture for Full Memory Safety
Yonghae Kim, Anurag Kar, Jaewon Lee +2
Despite decades of efforts to resolve, memory safety violations are still persistent and problematic in modern systems. Various defense mechanisms have been proposed, but their dep…
VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs
Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya +5
Deep Learning (DL) acceleration support in CPUs has recently gained a lot of traction, with several companies (Arm, Intel, IBM) announcing products with specialized matrix engines…
Revisiting Query Performance in GPU Database Systems
Jiashen Cao, Rathijit Sen, Matteo Interlandi +2
GPUs offer massive compute parallelism and high-bandwidth memory accesses. GPU database systems seek to exploit those capabilities to accelerate data analytics. Although modern GPU…
CuPBoP: CUDA for Parallelized and Broad-range Processors
Ruobing Han, Jun Chen, Bhanu Garg +3
CUDA is one of the most popular choices for GPU programming, but it can only be executed on NVIDIA GPUs. Executing CUDA on non-NVIDIA devices not only benefits the hardware communi…
COX: CUDA on X86 by Exposing Warp-Level Functions to CPUs
Ruobing Han, Jaewon Lee, Jaewoong Sim +1
As CUDA programs become the de facto program among data parallel applications such as high-performance computing or machine learning applications, running CUDA on other platforms h…
Vortex: Extending the RISC-V ISA for GPGPU and 3D-GraphicsResearch
Blaise Tine, Fares Elsabbagh, Krishna Yalamarthy +1
The importance of open-source hardware and software has been increasing. However, despite GPUs being one of the more popular accelerators across various applications, there is very…
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU
Geonhwa Jeong, Eric Qin, Ananda Samajdar +4
As AI-based applications become pervasive, CPU vendors are starting to incorporate matrix engines within the datapath to boost efficiency. Systolic arrays have been the premier arc…
Supporting CUDA for an extended RISC-V GPU architecture
Ruobing Han, Blaise Tine, Jaewon Lee +2
With the rapid development of scientific computation, more and more researchers and developers are committed to implementing various workloads/operations on different devices. Amon…
Context-Aware Task Handling in Resource-Constrained Robots with Virtualization
Ramyad Hadidi, Nima Shoghi Ghalehshahi, Bahar Asgari +1
Intelligent mobile robots are critical in several scenarios. However, as their computational resources are limited, mobile robots struggle to handle several tasks concurrently and…
Creating Robust Deep Neural Networks With Coded Distributed Computing for IoT Systems
Ramyad Hadidi, Jiashen Cao, Hyesoon Kim
The increasing interest in serverless computation and ubiquitous wireless networks has led to numerous connected devices in our surroundings. Among such devices, IoT devices have a…
THIA: Accelerating Video Analytics using Early Inference and Fine-Grained Query Planning
Jiashen Cao, Ramyad Hadidi, Joy Arulraj +1
To efficiently process visual data at scale, researchers have proposed two techniques for lowering the computational overhead associated with the underlying deep learning models. T…
Secure Location-Aware Authentication and Communication for Intelligent Transportation Systems
Nima Shoghi Ghalehshahi, Ramyad Hadidi, Lee Jaewon +6
Intelligent transportation systems (ITS) are expected to effectively create a stand-alone network for secure communication among autonomous agents. In such a dynamic and fast-chang…
Reducing Inference Latency with Concurrent Architectures for Image Recognition
Ramyad Hadidi, Jiashen Cao, Michael S. Ryoo +1
Satisfying the high computation demand of modern deep learning architectures is challenging for achieving low inference latency. The current approaches in decreasing latency only i…
Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads
Bahar Asgari, Ramyad Hadidi, Joshua Dierberger +3
Sparse matrices are the key ingredients of several application domains, from scientific computation to machine learning. The primary challenge with sparse matrices has been efficie…
LCP: A Low-Communication Parallelization Method for Fast Neural Network Inference in Image Recognition
Ramyad Hadidi, Bahar Asgari, Jiashen Cao +6
Deep neural networks (DNNs) have inspired new studies in myriad edge applications with robots, autonomous agents, and Internet-of-things (IoT) devices. However, performing inferenc…
Vortex: OpenCL Compatible RISC-V GPGPU
Fares Elsabbagh, Blaise Tine, Priyadarshini Roshan +6
The current challenges in technology scaling are pushing the semiconductor industry towards hardware specialization, creating a proliferation of heterogeneous systems-on-chip, deli…
A Case Study: Exploiting Neural Machine Translation to Translate CUDA to OpenCL
Yonghae Kim, Hyesoon Kim
The sequence-to-sequence (seq2seq) model for neural machine translation has significantly improved the accuracy of language translation. There have been new efforts to use this seq…
Collaborative Execution of Deep Neural Networks on Internet of Things Devices
Ramyad Hadidi, Jiashen Cao, Micheal S. Ryoo +1
With recent advancements in deep neural networks (DNNs), we are able to solve traditionally challenging problems. Since DNNs are compute intensive, consumers, to deploy a service,…
Musical Chair: Efficient Real-Time Recognition Using Collaborative IoT Devices
Ramyad Hadidi, Jiashen Cao, Matthew Woodward +2
The prevalence of Internet of things (IoT) devices and abundance of sensor data has created an increase in real-time data processing such as recognition of speech, image, and video…
Louvre: Lightweight Ordering Using Versioning for Release Consistency
Pranith Kumar, Prasun Gera, Hyojong Kim +1
Fence instructions are fundamental primitives that ensure consistency in a weakly consistent shared memory multi-core processor. The execution cost of these instructions is signifi…
Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube
Ramyad Hadidi, Bahar Asgari, Jeffrey Young +4
Memories that exploit three-dimensional (3D)-stacking technology, which integrate memory and logic dies in a single stack, are becoming popular. These memories, such as Hybrid Memo…
Demystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube
Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar +3
Three-dimensional (3D)-stacking technology, which enables the integration of DRAM and logic dies, offers high bandwidth and low energy consumption. This technology also empowers ne…
Inferring Fine-grained Control Flow Inside SGX Enclaves with Branch Shadowing
Sangho Lee, Ming-Wei Shih, Prasun Gera +3
In this paper, we explore a new, yet critical, side-channel attack against Intel Software Guard Extension (SGX), called a branch shadowing attack, which can reveal fine-grained con…