most citedAccelerating Training of Deep Neural Networks via Sparse Edge Processing

6 citations · 7 across the 2 of their papers we have counts for

collaborators

2 papers

cs.AR2019★ 1 cited

Automatic Conversion from Flip-flop to 3-phase Latch-based Designs

Huimei Cheng, Yichen Gu, Peter A. Beerel

Latch-based designs have many benefits over their flip-flop based counterparts but have limited use partially because most RTL specifications are flop-centric and automatic convers…

cs.NE2017★ 6 cited

Accelerating Training of Deep Neural Networks via Sparse Edge Processing

Sourya Dey, Yinan Shao, Keith M. Chugg +1

We propose a reconfigurable hardware architecture for deep neural networks (DNNs) capable of online training and inference, which uses algorithmically pre-determined, structured sp…