activity
20162026
most citedA Novel Side-Channel in Real-Time Schedulers

36 citations · 59 across the 11 of their papers we have counts for

collaborators

11 papers

cs.AR2026

A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs

Mohammed Sajjad Jafri, Abdur Rahman, Emon Sarkar +4

Hardware Performance Counters (HPCs) are widely used to enable event-driven software mechanisms such as profile guided optimization, performance analysis, and dynamic resource mana…

math.OC2025

Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for Multicore Real-Time Systems

Binqi Sun, Zhihang Wei, Andrea Bastoni +5

Memory bandwidth regulation and cache partitioning are widely used techniques for achieving predictable timing in real-time computing systems. Combined with partitioned scheduling,…

cs.AR2023★ 1 cited

Co-Optimizing Cache Partitioning and Multi-Core Task Scheduling: Exploit Cache Sensitivity or Not?

Binqi Sun, Debayan Roy, Tomasz Kloda +3

Cache partitioning techniques have been successfully adopted to mitigate interference among concurrently executing real-time tasks on multi-core processors. Considering that the ex…

cs.CR2020★ 1 cited

On Scheduler Side-Channels in Dynamic-Priority Real-Time Systems

Chien-Ying Chen, Sibin Mohan, Rodolfo Pellizzoni +1

While the existence of scheduler side-channels has been demonstrated recently for fixed-priority real-time systems (RTS), there have been no similar explorations for dynamic-priori…

cs.OS2019

Period Adaptation for Continuous Security Monitoring in Multicore Real-Time Systems

Monowar Hasan, Sibin Mohan, Rodolfo Pellizzoni +1

We propose a design-time framework (named HYDRA-C) for integrating security tasks into partitioned real-time systems (RTS) running on multicore platforms. Our goal is to opportunis…

cs.DC2018★ 1 cited

Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems

Ankit Agrawal, Renato Mancuso, Rodolfo Pellizzoni +1

One of the primary sources of unpredictability in modern multi-core embedded systems is contention over shared memory resources, such as caches, interconnects, and DRAM. Despite si…