5 papers
Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity
Fatemeh Sheikh Shoaei, Alireza Nahvy, Zainalabedin Navabi
This paper presents a design for test (DFT)architecture for fast and scalable testing of array multipliers (MULTs). Regardless of the MULT size, our proposed testable architecture,…
An Improved Scheme for Pre-computed Patterns in Core-based SoC Architecture
Elaheh Sadredini, Reza Rahimi, Paniz Foroutan +2
By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the incr…
BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding
Elaheh Sadredini, Mohammadreza Najafi, Mahmood Fathy +1
By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the incr…
Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint
Elaheh Sadredini, Mohammad Hashem Haghbayan, Mahmood Fathy +1
This paper presents a novel approach for test generation and test scheduling for multi-clock domain SoCs. A concurrent hybrid BIST architecture is proposed for testing cores. Furth…
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady +2
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futur…