52 citations · 584 across the 43 of their papers we have counts for
3 papers · 2 filters
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging
Satwik Patnaik, Mohammed Ashraf, Johann Knechtel +1
Layout camouflaging (LC) is a promising technique to protect chip design intellectual property (IP) from reverse engineers. Most prior art, however, cannot leverage the full potent…
On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity
Johann Knechtel, Ozgur Sinanoglu
Various side-channel attacks (SCAs) on ICs have been successfully demonstrated and also mitigated to some degree. In the context of 3D ICs, however, prior art has mainly focused on…
Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques
Abhrajit Sengupta, Satwik Patnaik, Johann Knechtel +3
Split manufacturing is a promising technique to defend against fab-based malicious activities such as IP piracy, overbuilding, and insertion of hardware Trojans. However, a network…