83 citations · 237 across the 12 of their papers we have counts for
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cs.DC2008
Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers
Georg Hager, Thomas Zeiser, Gerhard Wellein
Processor and system architectures that feature multiple memory controllers are prone to show bottlenecks and erratic performance numbers on codes with regular access patterns. Alt…
cs.DC2007
RZBENCH: Performance evaluation of current HPC architectures using low-level and application benchmarks
Georg Hager, Holger Stengel, Thomas Zeiser +1
RZBENCH is a benchmark suite that was specifically developed to reflect the requirements of scientific supercomputer users at the University of Erlangen-Nuremberg (FAU). It compris…