6 citations · 7 across the 4 of their papers we have counts for
4 papers
TDRAM: Tag-enhanced DRAM for Efficient Caching
Maryam Babaie, Ayaz Akram, Wendy Elsasser +6
As SRAM-based caches are hitting a scaling wall, manufacturers are integrating DRAM-based caches into system designs to continue increasing cache sizes. While DRAM caches can impro…
Enabling Design Space Exploration of DRAM Caches in Emerging Memory Systems
Maryam Babaie, Ayaz Akram, Jason Lowe-Power
The increasing growth of applications' memory capacity and performance demands has led the CPU vendors to deploy heterogeneous memory systems either within a single system or via d…
A Cycle-level Unified DRAM Cache Controller Model for 3DXPoint Memory Systems in gem5
Maryam Babaie, Ayaz Akram, Jason Lowe-Power
To accommodate the growing memory footprints of today's applications, CPU vendors have employed large DRAM caches, backed by large non-volatile memories like Intel Optane (e.g., In…
When to use 3D Die-Stacked Memory for Bandwidth-Constrained Big Data Workloads
Jason Lowe-Power, Mark D. Hill, David A. Wood
Response time requirements for big data processing systems are shrinking. To meet this strict response time requirement, many big data systems store all or most of their data in ma…