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cs.SE2025
HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis
Kangwei Xu, Bing Li, Grace Li Zhang +1
In high-level synthesis (HLS), C/C++ programs with synthesis directives are used to generate circuits for FPGA implementations. However, hardware-specific and platform-dependent ch…
cs.SE2024
CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design
Ruidi Qiu, Grace Li Zhang, Rolf Drechsler +2
Functional simulation is an essential step in digital hardware design. Recently, there has been a growing interest in leveraging Large Language Models (LLMs) for hardware testbench…
cs.SE2024
AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design
Ruidi Qiu, Grace Li Zhang, Rolf Drechsler +2
In digital circuit design, testbenches constitute the cornerstone of simulation-based hardware verification. Traditional methodologies for testbench generation during simulation-ba…