25 citations · 46 across the 7 of their papers we have counts for
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cs.AR2018
High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems
Rachata Ausavarungnirun, Gabriel H. Loh, Lavanya Subramanian +2
When multiple processor cores (CPUs) and a GPU integrated together on the same chip share the off-chip DRAM, requests from the GPU can heavily interfere with requests from the CPUs…
cs.AR2018★ 5 cited
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance
Rachata Ausavarungnirun, Saugata Ghose, Onur Kayıran +4
In a modern GPU architecture, all threads within a warp execute the same instruction in lockstep. For a memory instruction, this can lead to memory divergence: the memory requests…